From patchwork Fri Mar 30 12:51:46 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 149650 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 059A6B6EF4 for ; Sat, 31 Mar 2012 00:32:32 +1100 (EST) Received: from localhost ([::1]:34402 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDbKE-0003zd-Hd for incoming@patchwork.ozlabs.org; Fri, 30 Mar 2012 08:53:06 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33054) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDbJH-0001e7-Kk for qemu-devel@nongnu.org; Fri, 30 Mar 2012 08:52:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SDbJ8-0000CE-QT for qemu-devel@nongnu.org; Fri, 30 Mar 2012 08:52:07 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:41204) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDbJ8-0000Bv-IV for qemu-devel@nongnu.org; Fri, 30 Mar 2012 08:51:58 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SDbJ1-0000xW-4F; Fri, 30 Mar 2012 13:51:51 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 30 Mar 2012 13:51:46 +0100 Message-Id: <1333111910-3641-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333111910-3641-1-git-send-email-peter.maydell@linaro.org> References: <1333111910-3641-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Paul Brook , Anthony Liguori , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH 10/14] target-arm: Move OMAP cp15_i_{max, min} reset to cpu_state_reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset; since these registers are only accessible on CPUs with the OMAPCP feature set there's no need to guard this reset with either a CPUID or feature bit check. Signed-off-by: Peter Maydell --- target-arm/helper.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 6c21f74..a94f09f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -48,8 +48,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: - env->cp15.c15_i_max = 0x000; - env->cp15.c15_i_min = 0xff0; break; case ARM_CPUID_PXA250: case ARM_CPUID_PXA255: @@ -115,6 +113,7 @@ void cpu_state_reset(CPUARMState *env) env->cp15.c0_c2[3] = cpu->id_isar3; env->cp15.c0_c2[4] = cpu->id_isar4; env->cp15.c0_c2[5] = cpu->id_isar5; + env->cp15.c15_i_min = 0xff0; if (arm_feature(env, ARM_FEATURE_IWMMXT)) { env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';