From patchwork Tue Mar 27 09:24:40 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 148902 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 73364B6F62 for ; Tue, 27 Mar 2012 20:26:36 +1100 (EST) Received: from localhost ([::1]:47887 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCSff-0000JY-WD for incoming@patchwork.ozlabs.org; Tue, 27 Mar 2012 05:26:32 -0400 Received: from eggs.gnu.org ([208.118.235.92]:58813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCSfC-0007gE-3t for qemu-devel@nongnu.org; Tue, 27 Mar 2012 05:26:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SCSf4-00064G-Um for qemu-devel@nongnu.org; Tue, 27 Mar 2012 05:26:01 -0400 Received: from mail-iy0-f173.google.com ([209.85.210.173]:59991) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCSf4-0005ws-JO for qemu-devel@nongnu.org; Tue, 27 Mar 2012 05:25:54 -0400 Received: by mail-iy0-f173.google.com with SMTP id j26so11425942iaf.4 for ; Tue, 27 Mar 2012 02:25:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=chtpHvWFHZTKlMHoYxHa/CrzemvRcg/mzVMabRqsZpA=; b=gM9ur3UeMzKojlWo43u+jkVxTHzN7TaV93nm6cyKLSOEj2x3YYCJhl/9Wux2AoS2HQ 7LqKXNgiHf57q2PPtMBAZ/1Cv4LabwOlQbVZDxdwyH5M5gs0GftxmALmj0wxVR01r0At rsJTOSIm8yDkDU8qnPmJrbCDqJ39FpIBoarJ8hEcVJB2uahsa84pFGcqyzS5n6mAotyC F//09g83eCr0ejFLNpYd4ms3zbimpYpXhlRrdzrbcMv+5s/9KwmGaU4ol6CXuaCIBSTt b0kdOJ+bQy4SLLI3BVRKWhnIUkheFlkJaCYlrd2l98i8J9UeruREof0S3Z5jd678RM3R O/fA== Received: by 10.43.126.68 with SMTP id gv4mr14609633icc.30.1332840353876; Tue, 27 Mar 2012 02:25:53 -0700 (PDT) Received: from localhost ([1.202.183.51]) by mx.google.com with ESMTPS id nq4sm417109igc.5.2012.03.27.02.25.48 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 27 Mar 2012 02:25:52 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Tue, 27 Mar 2012 17:24:40 +0800 Message-Id: <1332840290-24553-3-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1332840290-24553-1-git-send-email-proljc@gmail.com> References: <1332840290-24553-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.173 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH V3 02/12] Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org There are 4 accumulator registers (acc) used by MIPS ASE DSP instructions. Each accumulator register is composed of by HIGH and LOW part. Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number (i.e. zero). Signed-off-by: Jia Liu Reviewed-by: Richard Henderson --- target-mips/translate.c | 56 ++++++++++++++++++++++++++++------------------ 1 files changed, 34 insertions(+), 22 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index a663b74..85a0998 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1972,6 +1972,7 @@ static void gen_shift (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg) { const char *opn = "hilo"; + unsigned int acc; if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { /* Treat as NOP. */ @@ -1980,25 +1981,29 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg) } switch (opc) { case OPC_MFHI: - tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]); + acc = ((ctx->opcode) >> 21) & 0x03; + tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]); opn = "mfhi"; break; case OPC_MFLO: - tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]); + acc = ((ctx->opcode) >> 21) & 0x03; + tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]); opn = "mflo"; break; case OPC_MTHI: + acc = ((ctx->opcode) >> 11) & 0x03; if (reg != 0) - tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]); + tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]); else - tcg_gen_movi_tl(cpu_HI[0], 0); + tcg_gen_movi_tl(cpu_HI[acc], 0); opn = "mthi"; break; case OPC_MTLO: + acc = ((ctx->opcode) >> 11) & 0x03; if (reg != 0) - tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]); + tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]); else - tcg_gen_movi_tl(cpu_LO[0], 0); + tcg_gen_movi_tl(cpu_LO[acc], 0); opn = "mtlo"; break; } @@ -2011,6 +2016,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { const char *opn = "mul/div"; TCGv t0, t1; + unsigned int acc; switch (opc) { case OPC_DIV: @@ -2073,6 +2079,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); + acc = (ctx->opcode >> 11) & 0x03; tcg_gen_ext_tl_i64(t2, t0); tcg_gen_ext_tl_i64(t3, t1); @@ -2082,8 +2089,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, tcg_gen_shri_i64(t2, t2, 32); tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[0], t0); - tcg_gen_ext32s_tl(cpu_HI[0], t1); + tcg_gen_ext32s_tl(cpu_LO[acc], t0); + tcg_gen_ext32s_tl(cpu_HI[acc], t1); } opn = "mult"; break; @@ -2091,6 +2098,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); + acc = (ctx->opcode >> 11) & 0x03; tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); @@ -2102,8 +2110,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, tcg_gen_shri_i64(t2, t2, 32); tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[0], t0); - tcg_gen_ext32s_tl(cpu_HI[0], t1); + tcg_gen_ext32s_tl(cpu_LO[acc], t0); + tcg_gen_ext32s_tl(cpu_HI[acc], t1); } opn = "multu"; break; @@ -2150,19 +2158,20 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); + acc = (ctx->opcode >> 11) & 0x03; tcg_gen_ext_tl_i64(t2, t0); tcg_gen_ext_tl_i64(t3, t1); tcg_gen_mul_i64(t2, t2, t3); - tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); tcg_temp_free_i64(t3); tcg_gen_trunc_i64_tl(t0, t2); tcg_gen_shri_i64(t2, t2, 32); tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[0], t0); - tcg_gen_ext32s_tl(cpu_HI[0], t1); + tcg_gen_ext32s_tl(cpu_LO[acc], t0); + tcg_gen_ext32s_tl(cpu_HI[acc], t1); } opn = "madd"; break; @@ -2170,21 +2179,22 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); + acc = (ctx->opcode) & 0x03; tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); tcg_gen_extu_tl_i64(t2, t0); tcg_gen_extu_tl_i64(t3, t1); tcg_gen_mul_i64(t2, t2, t3); - tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); tcg_temp_free_i64(t3); tcg_gen_trunc_i64_tl(t0, t2); tcg_gen_shri_i64(t2, t2, 32); tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[0], t0); - tcg_gen_ext32s_tl(cpu_HI[0], t1); + tcg_gen_ext32s_tl(cpu_LO[acc], t0); + tcg_gen_ext32s_tl(cpu_HI[acc], t1); } opn = "maddu"; break; @@ -2192,19 +2202,20 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); + acc = (ctx->opcode >> 11) & 0x03; tcg_gen_ext_tl_i64(t2, t0); tcg_gen_ext_tl_i64(t3, t1); tcg_gen_mul_i64(t2, t2, t3); - tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); tcg_temp_free_i64(t3); tcg_gen_trunc_i64_tl(t0, t2); tcg_gen_shri_i64(t2, t2, 32); tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[0], t0); - tcg_gen_ext32s_tl(cpu_HI[0], t1); + tcg_gen_ext32s_tl(cpu_LO[acc], t0); + tcg_gen_ext32s_tl(cpu_HI[acc], t1); } opn = "msub"; break; @@ -2212,21 +2223,22 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); + acc = (ctx->opcode >> 11) & 0x03; tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); tcg_gen_extu_tl_i64(t2, t0); tcg_gen_extu_tl_i64(t3, t1); tcg_gen_mul_i64(t2, t2, t3); - tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); tcg_temp_free_i64(t3); tcg_gen_trunc_i64_tl(t0, t2); tcg_gen_shri_i64(t2, t2, 32); tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[0], t0); - tcg_gen_ext32s_tl(cpu_HI[0], t1); + tcg_gen_ext32s_tl(cpu_LO[acc], t0); + tcg_gen_ext32s_tl(cpu_HI[acc], t1); } opn = "msubu"; break;