From patchwork Wed Mar 14 21:42:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 146787 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 29398B6EEF for ; Thu, 15 Mar 2012 10:49:45 +1100 (EST) Received: from localhost ([::1]:34229 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7vzN-0006DT-FV for incoming@patchwork.ozlabs.org; Wed, 14 Mar 2012 17:44:09 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45392) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7vyk-00055M-81 for qemu-devel@nongnu.org; Wed, 14 Mar 2012 17:43:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7vya-0005g0-8i for qemu-devel@nongnu.org; Wed, 14 Mar 2012 17:43:29 -0400 Received: from cantor2.suse.de ([195.135.220.15]:34932 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7vyZ-0005f1-VE for qemu-devel@nongnu.org; Wed, 14 Mar 2012 17:43:20 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id C88FB9043F for ; Wed, 14 Mar 2012 22:43:18 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Wed, 14 Mar 2012 22:42:39 +0100 Message-Id: <1331761376-20362-27-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1331761376-20362-1-git-send-email-afaerber@suse.de> References: <1331761376-20362-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH v5 26/43] arm-semi: Don't use CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Scripted conversion: sed -i "s/CPUState/CPUARMState/g" arm-semi.c Signed-off-by: Andreas Färber Acked-by: Anthony Liguori --- arm-semi.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arm-semi.c b/arm-semi.c index 873518a..8debd19 100644 --- a/arm-semi.c +++ b/arm-semi.c @@ -108,7 +108,7 @@ static inline uint32_t set_swi_errno(TaskState *ts, uint32_t code) return code; } #else -static inline uint32_t set_swi_errno(CPUState *env, uint32_t code) +static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) { return code; } @@ -122,7 +122,7 @@ static target_ulong arm_semi_syscall_len; static target_ulong syscall_err; #endif -static void arm_semi_cb(CPUState *env, target_ulong ret, target_ulong err) +static void arm_semi_cb(CPUARMState *env, target_ulong ret, target_ulong err) { #ifdef CONFIG_USER_ONLY TaskState *ts = env->opaque; @@ -152,7 +152,7 @@ static void arm_semi_cb(CPUState *env, target_ulong ret, target_ulong err) } } -static void arm_semi_flen_cb(CPUState *env, target_ulong ret, target_ulong err) +static void arm_semi_flen_cb(CPUARMState *env, target_ulong ret, target_ulong err) { /* The size is always stored in big-endian order, extract the value. We assume the size always fit in 32 bits. */ @@ -174,7 +174,7 @@ static void arm_semi_flen_cb(CPUState *env, target_ulong ret, target_ulong err) __arg; \ }) #define SET_ARG(n, val) put_user_ual(val, args + (n) * 4) -uint32_t do_arm_semihosting(CPUState *env) +uint32_t do_arm_semihosting(CPUARMState *env) { target_ulong args; char * s; @@ -184,7 +184,7 @@ uint32_t do_arm_semihosting(CPUState *env) #ifdef CONFIG_USER_ONLY TaskState *ts = env->opaque; #else - CPUState *ts = env; + CPUARMState *ts = env; #endif nr = env->regs[0];