From patchwork Sat Mar 10 16:53:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 145888 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D6BD3B6FA8 for ; Sun, 11 Mar 2012 05:24:55 +1100 (EST) Received: from localhost ([::1]:43148 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PZ7-0007pg-KM for incoming@patchwork.ozlabs.org; Sat, 10 Mar 2012 11:54:45 -0500 Received: from eggs.gnu.org ([208.118.235.92]:41630) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PYc-0006cm-Fb for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6PYa-0001Xs-Ay for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:14 -0500 Received: from cantor2.suse.de ([195.135.220.15]:42675 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PYa-0001Ue-11 for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:12 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id D06D6A0FEE; Sat, 10 Mar 2012 17:54:10 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sat, 10 Mar 2012 17:53:54 +0100 Message-Id: <1331398436-20761-19-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1331398436-20761-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331398436-20761-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [Qemu-devel] [PATCH RFC v4 18/20] target-arm: Add cpuid-{variant, revision} properties to CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Allow to inspect and manipulate MIDR variant and revision fields. Signed-off-by: Andreas Färber Cc: Peter Maydell --- target-arm/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 48 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 8917a20..ad33742 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -20,6 +20,7 @@ #include "cpu-qom.h" #include "qemu-common.h" +#include "qapi/qapi-visit-core.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #endif @@ -173,6 +174,46 @@ static inline void unset_class_feature(ARMCPUClass *klass, int feature) klass->features &= ~(1u << feature); } +static void arm_cpuid_variant_get(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + int64_t value = (cpu->env.cp15.c0_cpuid >> 20) & 0xf; + + visit_type_int(v, &value, name, errp); +} + +static void arm_cpuid_variant_set(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + int64_t value; + + visit_type_int(v, &value, name, errp); + cpu->env.cp15.c0_cpuid &= ~(0xf << 20); + cpu->env.cp15.c0_cpuid |= (value << 20) & 0xf; +} + +static void arm_cpuid_revision_get(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + int64_t value = cpu->env.cp15.c0_cpuid & 0xf; + + visit_type_int(v, &value, name, errp); +} + +static void arm_cpuid_revision_set(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + int64_t value; + + visit_type_int(v, &value, name, errp); + cpu->env.cp15.c0_cpuid &= ~0xf; + cpu->env.cp15.c0_cpuid |= value & 0xf; +} + /* CPU models */ typedef struct ARMCPUInfo { @@ -554,6 +595,13 @@ static void arm_cpu_initfn(Object *obj) cpu->env.cp15.c0_cpuid = cpu_class->cp15.c0_cpuid; cpu_reset(CPU(cpu)); + + object_property_add(obj, "cpuid-variant", "uint4", + arm_cpuid_variant_get, + arm_cpuid_variant_set, NULL, NULL, NULL); + object_property_add(obj, "cpuid-revision", "uint4", + arm_cpuid_revision_get, + arm_cpuid_revision_set, NULL, NULL, NULL); } static void arm_cpu_class_init(ObjectClass *klass, void *data)