From patchwork Sat Feb 18 17:11:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 142045 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A905CB6EE7 for ; Sun, 19 Feb 2012 05:16:49 +1100 (EST) Received: from localhost ([::1]:56962 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rynpy-0005Dz-Uv for incoming@patchwork.ozlabs.org; Sat, 18 Feb 2012 12:12:42 -0500 Received: from eggs.gnu.org ([140.186.70.92]:50307) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rynpd-0004eh-VW for qemu-devel@nongnu.org; Sat, 18 Feb 2012 12:12:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rynpa-0005pX-Qn for qemu-devel@nongnu.org; Sat, 18 Feb 2012 12:12:20 -0500 Received: from mail-bk0-f45.google.com ([209.85.214.45]:63774) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rynpa-0005kY-27 for qemu-devel@nongnu.org; Sat, 18 Feb 2012 12:12:18 -0500 Received: by mail-bk0-f45.google.com with SMTP id e19so4291536bku.4 for ; Sat, 18 Feb 2012 09:12:17 -0800 (PST) Received-SPF: pass (google.com: domain of jcmvbkbc@gmail.com designates 10.204.156.77 as permitted sender) client-ip=10.204.156.77; Authentication-Results: mr.google.com; spf=pass (google.com: domain of jcmvbkbc@gmail.com designates 10.204.156.77 as permitted sender) smtp.mail=jcmvbkbc@gmail.com; dkim=pass header.i=jcmvbkbc@gmail.com Received: from mr.google.com ([10.204.156.77]) by 10.204.156.77 with SMTP id v13mr7876746bkw.112.1329585137464 (num_hops = 1); Sat, 18 Feb 2012 09:12:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=6L1fmUSw89AFDXKjG5i+2oItHd9d4/MZbrkpzDu9X78=; b=M5qAYSW4MwALeHmOD9cwboVds1NFtxTiNkdx+5LIYvGhMAaHmYi1DtdxQpAj9hg60W p1FZcK1XjiGWTmyRWKzY+qNnVQin6hrBrZ4hE+1xqX3amQRbh8W1JLx7zR9ZmSG/Gm6q wPoPjKi3ysVMwdRZTit6cRKASYxQAtxHq30tA= Received: by 10.204.156.77 with SMTP id v13mr6404380bkw.112.1329585137378; Sat, 18 Feb 2012 09:12:17 -0800 (PST) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id o7sm28887600bkw.16.2012.02.18.09.12.15 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 18 Feb 2012 09:12:16 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Sat, 18 Feb 2012 21:11:37 +0400 Message-Id: <1329585103-31371-6-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1329585103-31371-1-git-send-email-jcmvbkbc@gmail.com> References: <1329564636-29883-1-git-send-email-jcmvbkbc@gmail.com> <1329585103-31371-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.214.45 Cc: blauwirbel@gmail.com, Max Filippov , aliguori@us.ibm.com, afaerber@suse.de Subject: [Qemu-devel] [PATCH 06/12] target-xtensa: add ICOUNT SR and debug exception X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org ICOUNT SR gets incremented on every instruction completion provided that CINTLEVEL at the beginning of the instruction execution is lower than ICOUNTLEVEL. When ICOUNT would increment to 0 a debug exception is raised if CINTLEVEL is lower than DEBUGLEVEL. See ISA, 4.7.7.5 for more details. Signed-off-by: Max Filippov --- target-xtensa/cpu.h | 6 +++++ target-xtensa/translate.c | 49 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 1 deletions(-) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index a18072b..92441e3 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -142,6 +142,8 @@ enum { DEBUGCAUSE = 233, CCOUNT = 234, PRID = 235, + ICOUNT = 236, + ICOUNTLEVEL = 237, EXCVADDR = 238, CCOMPARE = 240, }; @@ -429,6 +431,7 @@ static inline int cpu_mmu_index(CPUState *env) #define XTENSA_TBFLAG_EXCM 0x4 #define XTENSA_TBFLAG_LITBASE 0x8 #define XTENSA_TBFLAG_DEBUG 0x10 +#define XTENSA_TBFLAG_ICOUNT 0x20 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, target_ulong *cs_base, int *flags) @@ -448,6 +451,9 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, if (xtensa_get_cintlevel(env) < env->config->debug_level) { *flags |= XTENSA_TBFLAG_DEBUG; } + if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { + *flags |= XTENSA_TBFLAG_ICOUNT; + } } } diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index a438474..3bf880f 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -63,6 +63,8 @@ typedef struct DisasContext { unsigned used_window; bool debug; + bool icount; + TCGv_i32 next_icount; } DisasContext; static TCGv_ptr cpu_env; @@ -127,6 +129,8 @@ static const char * const sregnames[256] = { [DEBUGCAUSE] = "DEBUGCAUSE", [CCOUNT] = "CCOUNT", [PRID] = "PRID", + [ICOUNT] = "ICOUNT", + [ICOUNTLEVEL] = "ICOUNTLEVEL", [EXCVADDR] = "EXCVADDR", [CCOMPARE] = "CCOMPARE0", [CCOMPARE + 1] = "CCOMPARE1", @@ -313,10 +317,13 @@ static void gen_check_privilege(DisasContext *dc) static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) { tcg_gen_mov_i32(cpu_pc, dest); + gen_advance_ccount(dc); + if (dc->icount) { + tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); + } if (dc->singlestep_enabled) { gen_exception(dc, EXCP_DEBUG); } else { - gen_advance_ccount(dc); if (slot >= 0) { tcg_gen_goto_tb(slot); tcg_gen_exit_tb((tcg_target_long)dc->tb + slot); @@ -580,6 +587,22 @@ static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v) { } +static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v) +{ + if (dc->icount) { + tcg_gen_mov_i32(dc->next_icount, v); + } else { + tcg_gen_mov_i32(cpu_SR[sr], v); + } +} + +static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v) +{ + tcg_gen_andi_i32(cpu_SR[sr], v, 0xf); + /* This can change tb->flags, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); +} + static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v) { uint32_t id = sr - CCOMPARE; @@ -617,6 +640,8 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) [PS] = gen_wsr_ps, [DEBUGCAUSE] = gen_wsr_debugcause, [PRID] = gen_wsr_prid, + [ICOUNT] = gen_wsr_icount, + [ICOUNTLEVEL] = gen_wsr_icountlevel, [CCOMPARE] = gen_wsr_ccompare, [CCOMPARE + 1] = gen_wsr_ccompare, [CCOMPARE + 2] = gen_wsr_ccompare, @@ -2493,10 +2518,14 @@ static void gen_intermediate_code_internal( dc.is_jmp = DISAS_NEXT; dc.ccount_delta = 0; dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG; + dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT; init_litbase(&dc); init_sar_tracker(&dc); reset_used_window(&dc); + if (dc.icount) { + dc.next_icount = tcg_temp_local_new_i32(); + } gen_icount_start(); @@ -2532,12 +2561,27 @@ static void gen_intermediate_code_internal( gen_io_start(); } + if (dc.icount) { + int label = gen_new_label(); + + tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1); + tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label); + tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]); + if (dc.debug) { + gen_debug_exception(&dc, DEBUGCAUSE_IC); + } + gen_set_label(label); + } + if (dc.debug) { gen_ibreak_check(env, &dc); } disas_xtensa_insn(&dc); ++insn_count; + if (dc.icount) { + tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); + } if (env->singlestep_enabled) { tcg_gen_movi_i32(cpu_pc, dc.pc); gen_exception(&dc, EXCP_DEBUG); @@ -2550,6 +2594,9 @@ static void gen_intermediate_code_internal( reset_litbase(&dc); reset_sar_tracker(&dc); + if (dc.icount) { + tcg_temp_free(dc.next_icount); + } if (tb->cflags & CF_LAST_IO) { gen_io_end();