@@ -9,7 +9,7 @@
stepping = "3"
feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
feature_ecx = "ssse3 sse3"
- extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+ extfeature_edx = "i64 xd syscall"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"
@@ -23,7 +23,7 @@
stepping = "3"
feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
feature_ecx = "sse4.1 cx16 ssse3 sse3"
- extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+ extfeature_edx = "i64 xd syscall"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"
@@ -37,7 +37,7 @@
stepping = "3"
feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
- extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu"
+ extfeature_edx = "i64 syscall xd"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
This patch removes the replicated feature flags from cpuid 8000_0001:edx (extfeature_edx) from Intel models, as the duplicated feature flags are present only on AMD CPUs. On Intel models, only the i64, syscall, and xd flags are kept on extfeature_edx. This is based on a previous patch from John Cooper where this was introduced with many other changes at the same time. Original John's patch submission is at Message-ID: <4DDAD5E7.2020002@redhat.com>, <http://marc.info/?l=qemu-devel&m=130618871926030>. Original John's patch description was: cpu model bug fixes and definition corrections This patch was intended to address the replicated feature flags in cpuid 8000_0001:edx from cpuid 0000_0001:edx. This is due to AMD's definition where these flags are mostly cloned in the 8000_0001:edx cpuid function. qemu64 attempted to glue together the respective Intel and AMD nearly disjoint features and this propagated to the new Intel models as doing so was believed conservative at the time. However after further soak and test lugging around this cruft doesn't provide any value, could conceivably confuse a guest, and has confused users trying to maintain/add cpu definitions. This also caused issues for libvirt attempting to track this mis-encoding. So we've here tossed out the AMD replicated definitions from the Intel models, added a few replications into AMD definitions which were missing according to AMD's latest CPUID document, and reordered the config file flags to follow intuitive sequential bit ordering. Also two flag name aliases were added for clarity to Intel models. The end result being the models definitions now conform to their respective cpuid specifications sans x2apic which is emulated by kvm. This was tested with the following combinations: [Conroe, Penryn, Nehalem] x [F12-64, win64, win32] -- Intel host [Opteron_G1, Opteron_G2, Opteron_G3] x [F12-64, win64, win32] -- AMD host Yielding successful boots in all cases. Signed-off-by: john cooper <john.cooper@redhat.com> Changes v1 -> v2: - Rebase against latest Qemu git tree Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- sysconfigs/target/target-x86_64.conf | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)