From patchwork Sun Jan 8 23:52:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 134955 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 42333B6F69 for ; Mon, 9 Jan 2012 10:52:08 +1100 (EST) Received: from localhost ([::1]:60685 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rk2Wz-0007qd-H6 for incoming@patchwork.ozlabs.org; Sun, 08 Jan 2012 18:52:05 -0500 Received: from eggs.gnu.org ([140.186.70.92]:35837) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rk2Wh-0006sh-3g for qemu-devel@nongnu.org; Sun, 08 Jan 2012 18:51:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rk2Wf-0002tj-Dl for qemu-devel@nongnu.org; Sun, 08 Jan 2012 18:51:47 -0500 Received: from cantor2.suse.de ([195.135.220.15]:44863 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rk2Wf-0002tR-1D for qemu-devel@nongnu.org; Sun, 08 Jan 2012 18:51:45 -0500 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 6B39E8FD0F; Mon, 9 Jan 2012 00:51:44 +0100 (CET) From: Alexander Graf To: "qemu-devel@nongnu.org Developers" Date: Mon, 9 Jan 2012 00:52:38 +0100 Message-Id: <1326066759-8210-1-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.7.3.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Avi Kivity , kvm list Subject: [Qemu-devel] [PATCH 1/2] KVM: Add new -cpu best X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org During discussions on whether to make -cpu host the default in SLE, I found myself disagreeing to the thought, because it potentially opens a big can of worms for potential bugs. But if I already am so opposed to it for SLE, how can it possibly be reasonable to default to -cpu host in upstream QEMU? And what would a sane default look like? So I had this idea of looping through all available CPU definitions. We can pretty well tell if our host is able to execute any of them by checking the respective flags and seeing if our host has all features the CPU definition requires. With that, we can create a -cpu type that would fall back to the "best known CPU definition" that our host can fulfill. On my Phenom II system for example, that would be -cpu phenom. With this approach we can test and verify that CPU types actually work at any random user setup, because we can always verify that all the -cpu types we ship actually work. And we only default to some clever mechanism that chooses from one of these. Signed-off-by: Alexander Graf --- target-i386/cpuid.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 81 insertions(+), 0 deletions(-) diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c index 91a104b..b2e3420 100644 --- a/target-i386/cpuid.c +++ b/target-i386/cpuid.c @@ -550,6 +550,85 @@ static int cpu_x86_fill_host(x86_def_t *x86_cpu_def) return 0; } +/* Are all guest feature bits present on the host? */ +static bool cpu_x86_feature_subset(uint32_t host, uint32_t guest) +{ + int i; + + for (i = 0; i < 32; i++) { + uint32_t mask = 1 << i; + if ((guest & mask) && !(host & mask)) { + return false; + } + } + + return true; +} + +/* Does the host support all the features of the CPU definition? */ +static bool cpu_x86_fits_host(x86_def_t *x86_cpu_def) +{ + uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; + + host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); + if (x86_cpu_def->level > eax) { + return false; + } + if ((x86_cpu_def->vendor1 != ebx) || + (x86_cpu_def->vendor2 != edx) || + (x86_cpu_def->vendor3 != ecx)) { + return false; + } + + host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); + if (!cpu_x86_feature_subset(ecx, x86_cpu_def->ext_features) || + !cpu_x86_feature_subset(edx, x86_cpu_def->features)) { + return false; + } + + host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx); + if (x86_cpu_def->xlevel > eax) { + return false; + } + + host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx); + if (!cpu_x86_feature_subset(edx, x86_cpu_def->ext2_features) || + !cpu_x86_feature_subset(ecx, x86_cpu_def->ext3_features)) { + return false; + } + + return true; +} + +/* Returns true when new_def is higher versioned than old_def */ +static int cpu_x86_fits_higher(x86_def_t *new_def, x86_def_t *old_def) +{ + int old_fammod = (old_def->family << 24) | (old_def->model << 8) + | (old_def->stepping); + int new_fammod = (new_def->family << 24) | (new_def->model << 8) + | (new_def->stepping); + + return new_fammod > old_fammod; +} + +static void cpu_x86_fill_best(x86_def_t *x86_cpu_def) +{ + x86_def_t *def; + + x86_cpu_def->family = 0; + x86_cpu_def->model = 0; + for (def = x86_defs; def; def = def->next) { + if (cpu_x86_fits_host(def) && cpu_x86_fits_higher(def, x86_cpu_def)) { + memcpy(x86_cpu_def, def, sizeof(*def)); + } + } + + if (!x86_cpu_def->family && !x86_cpu_def->model) { + fprintf(stderr, "No fitting CPU model found!\n"); + exit(1); + } +} + static int unavailable_host_feature(struct model_features_t *f, uint32_t mask) { int i; @@ -617,6 +696,8 @@ static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model) break; if (kvm_enabled() && name && strcmp(name, "host") == 0) { cpu_x86_fill_host(x86_cpu_def); + } else if (kvm_enabled() && name && strcmp(name, "best") == 0) { + cpu_x86_fill_best(x86_cpu_def); } else if (!def) { goto error; } else {