From patchwork Thu Dec 29 16:19:51 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Langsdorf X-Patchwork-Id: 133580 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1AFBAB6FBB for ; Fri, 30 Dec 2011 04:04:35 +1100 (EST) Received: from localhost ([::1]:60936 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgIj4-0007KC-AO for incoming@patchwork.ozlabs.org; Thu, 29 Dec 2011 11:21:06 -0500 Received: from eggs.gnu.org ([140.186.70.92]:49877) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgIiC-0005U4-RN for qemu-devel@nongnu.org; Thu, 29 Dec 2011 11:20:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RgIi2-0007mh-Lu for qemu-devel@nongnu.org; Thu, 29 Dec 2011 11:20:12 -0500 Received: from smtp151.dfw.emailsrvr.com ([67.192.241.151]:43701) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgIi2-0007mU-EO for qemu-devel@nongnu.org; Thu, 29 Dec 2011 11:20:02 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp5.relay.dfw1a.emailsrvr.com (SMTP Server) with ESMTP id 59F16585A7; Thu, 29 Dec 2011 11:20:00 -0500 (EST) X-Virus-Scanned: OK Received: by smtp5.relay.dfw1a.emailsrvr.com (Authenticated sender: mark.langsdorf-AT-calxeda.com) with ESMTPSA id 16AF7581DD; Thu, 29 Dec 2011 11:20:00 -0500 (EST) From: Mark Langsdorf To: qemu-devel@nongnu.org Date: Thu, 29 Dec 2011 10:19:51 -0600 Message-Id: <1325175596-5807-3-git-send-email-mark.langsdorf@calxeda.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1325175596-5807-1-git-send-email-mark.langsdorf@calxeda.com> References: <1325175596-5807-1-git-send-email-mark.langsdorf@calxeda.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 67.192.241.151 Cc: peter.maydell@linaro.org, Mark Langsdorf , afaerber@suse.de, rob.herring@calxeda.com Subject: [Qemu-devel] =?utf-8?q?=5BPATCH_v5_2/7=5D_arm=3A_Set_frequencies_?= =?utf-8?q?for_arm=5Ftimer?= X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use qdev properties to allow board modelers to set the frequencies for the sp804 timer. Each of the sp804's timers can have an individual frequency. The timers default to 1MHz. Signed-off-by: Mark Langsdorf Reviewed-by: Peter Maydell Reviewed-by: Andreas Färber --- Changes from v3, v4 None Changes from v2 Comment correctly describes behavior of properties freqX variables are defined as uint32_t, not int Changes from v1 Simplified multiple timer frequency handling Removed the shared default hw/arm_timer.c | 24 +++++++++++++++++++----- 1 files changed, 19 insertions(+), 5 deletions(-) diff --git a/hw/arm_timer.c b/hw/arm_timer.c index 0a5b9d2..60e1c63 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -9,6 +9,8 @@ #include "sysbus.h" #include "qemu-timer.h" +#include "qemu-common.h" +#include "qdev.h" /* Common timer implementation. */ @@ -178,6 +180,7 @@ typedef struct { SysBusDevice busdev; MemoryRegion iomem; arm_timer_state *timer[2]; + uint32_t freq0, freq1; int level[2]; qemu_irq irq; } sp804_state; @@ -269,10 +272,11 @@ static int sp804_init(SysBusDevice *dev) qi = qemu_allocate_irqs(sp804_set_irq, s, 2); sysbus_init_irq(dev, &s->irq); - /* ??? The timers are actually configurable between 32kHz and 1MHz, but - we don't implement that. */ - s->timer[0] = arm_timer_init(1000000); - s->timer[1] = arm_timer_init(1000000); + /* The timers are configurable between 32kHz and 1MHz + * defaulting to 1MHz but overrideable as individual properties */ + s->timer[0] = arm_timer_init(s->freq0); + s->timer[1] = arm_timer_init(s->freq1); + s->timer[0]->irq = qi[0]; s->timer[1]->irq = qi[1]; memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000); @@ -281,6 +285,16 @@ static int sp804_init(SysBusDevice *dev) return 0; } +static SysBusDeviceInfo sp804_info = { + .init = sp804_init, + .qdev.name = "sp804", + .qdev.size = sizeof(sp804_state), + .qdev.props = (Property[]) { + DEFINE_PROP_UINT32("freq0", sp804_state, freq0, 1000000), + DEFINE_PROP_UINT32("freq1", sp804_state, freq1, 1000000), + DEFINE_PROP_END_OF_LIST(), + } +}; /* Integrator/CP timer module. */ @@ -349,7 +363,7 @@ static int icp_pit_init(SysBusDevice *dev) static void arm_timer_register_devices(void) { sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init); - sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init); + sysbus_register_withprop(&sp804_info); } device_init(arm_timer_register_devices)