From patchwork Sat Oct 22 10:11:13 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khansa Butt X-Patchwork-Id: 121177 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E155C1007D3 for ; Sat, 22 Oct 2011 21:31:50 +1100 (EST) Received: from localhost ([::1]:46484 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RHYrk-0000cP-1s for incoming@patchwork.ozlabs.org; Sat, 22 Oct 2011 06:31:48 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47230) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RHYNB-0000rC-Tb for qemu-devel@nongnu.org; Sat, 22 Oct 2011 06:00:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RHYN2-0006kM-CX for qemu-devel@nongnu.org; Sat, 22 Oct 2011 06:00:08 -0400 Received: from mail-wy0-f173.google.com ([74.125.82.173]:39457) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RHYN2-0006Q2-0V for qemu-devel@nongnu.org; Sat, 22 Oct 2011 06:00:04 -0400 Received: by mail-wy0-f173.google.com with SMTP id 15so5354962wyh.4 for ; Sat, 22 Oct 2011 03:00:03 -0700 (PDT) Received: by 10.216.131.161 with SMTP id m33mr1242563wei.55.1319277602568; Sat, 22 Oct 2011 03:00:02 -0700 (PDT) Received: from localhost.localdomain ([111.68.102.16]) by mx.google.com with ESMTPS id e7sm26686750wbh.12.2011.10.22.02.59.59 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 22 Oct 2011 03:00:02 -0700 (PDT) From: khansa@kics.edu.pk To: qemu-devel@nongnu.org Date: Sat, 22 Oct 2011 15:11:13 +0500 Message-Id: <1319278273-32437-7-git-send-email-khansa@kics.edu.pk> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1319278273-32437-1-git-send-email-khansa@kics.edu.pk> References: <1319278273-32437-1-git-send-email-khansa@kics.edu.pk> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.173 Cc: peter.maydell@linaro.org, riku.voipio@iki.fi, Khansa Butt , aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v3 6/6] Addition of Cavium instructions in disassembler X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Khansa Butt Signed-off-by: Khansa Butt --- mips-dis.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 53 insertions(+), 0 deletions(-) diff --git a/mips-dis.c b/mips-dis.c index e3a6e0b..96ab1e8 100644 --- a/mips-dis.c +++ b/mips-dis.c @@ -300,6 +300,7 @@ struct mips_opcode Also used for immediate operands in vr5400 vector insns. "o" 16 bit signed offset (OP_*_DELTA) "p" 16 bit PC relative branch target address (OP_*_DELTA) + "+p" 5 bit unsigned constant describing bit position, for Octeon (OP_*_RT) "q" 10 bit extra breakpoint code (OP_*_CODE2) "r" 5 bit same register used as both source and target (OP_*_RS) "s" 5 bit source register specifier (OP_*_RS) @@ -491,6 +492,13 @@ struct mips_opcode #define INSN_MULT 0x40000000 /* Instruction synchronize shared memory. */ #define INSN_SYNC 0x80000000 +/* Load Cavium specific multiplier registers. */ +#define INSN_WRITE_MPL0 0x100000000 +#define INSN_WRITE_MPL1 0x200000000 +#define INSN_WRITE_MPL2 0x400000000 +#define INSN_WRITE_P0 0x800000000 +#define INSN_WRITE_P1 0x1000000000 +#define INSN_WRITE_P2 0x2000000000 /* These are the bits which may be set in the pinfo2 field of an instruction. */ @@ -569,6 +577,8 @@ struct mips_opcode #define INSN_LOONGSON_2E 0x40000000 /* ST Microelectronics Loongson 2F. */ #define INSN_LOONGSON_2F 0x80000000 +/* Cavium Network's Octeon processor */ +#define INSN_CVM_OCTEON 0x100000000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -1099,6 +1109,13 @@ extern const int bfd_mips16_num_opcodes; #define RD_HI INSN_READ_HI #define MOD_HI WR_HI|RD_HI +#define WR_MPL0 INSN_WRITE_MPL0 +#define WR_MPL1 INSN_WRITE_MPL1 +#define WR_MPL2 INSN_WRITE_MPL2 +#define WR_P0 INSN_WRITE_P0 +#define WR_P1 INSN_WRITE_P1 +#define WR_P2 INSN_WRITE_P2 + #define WR_LO INSN_WRITE_LO #define RD_LO INSN_READ_LO #define MOD_LO WR_LO|RD_LO @@ -1137,6 +1154,8 @@ extern const int bfd_mips16_num_opcodes; #define IL2E (INSN_LOONGSON_2E) #define IL2F (INSN_LOONGSON_2F) +#define ICVM (INSN_CVM_OCTEON) + #define P3 INSN_4650 #define L1 INSN_4010 #define V1 (INSN_4100 | INSN_4111 | INSN_4120) @@ -2435,6 +2454,34 @@ const struct mips_opcode mips_builtin_opcodes[] = {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 }, {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 }, {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }, +/* Cavium specific instructions */ +{"baddu", "d,s,t", 0x70000028, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM }, +{"dmul", "d,s,t", 0x70000003, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM }, +{"v3mulu", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM }, +{"vmm0", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM }, +{"vmulu", "d,s,t", 0x7000000f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM }, +{"seq", "d,s,t", 0x7000002a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM }, +{"seqi", "t,r,j", 0x7000002e, 0xfc00003f, WR_t|RD_s, 0, ICVM }, +{"sne", "d,s,t", 0x7000002b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, ICVM }, +{"snei", "t,r,j", 0x7000002f, 0xfc00003f, WR_t|RD_s, 0, ICVM }, +{"bbit0", "s,+p,p", 0xc8000000, 0xfc000000, CBD|RD_s, 0, ICVM }, +{"bbit032", "s,+p,p", 0xd8000000, 0xfc000000, CBD|RD_s, 0, ICVM }, +{"bbit1", "s,+p,p", 0xe8000000, 0xfc000000, CBD|RD_s, 0, ICVM }, +{"bbit132", "s,+p,p", 0xf8000000, 0xfc000000, CBD|RD_s, 0, ICVM }, +{"saa", "t,(b)", 0x70000018, 0xfc00ffff, SM|RD_t|RD_b, 0, ICVM }, +{"saad", "t,(b)", 0x70000019, 0xfc00ffff, SM|RD_t|RD_b, 0, ICVM }, +{"exts", "t,r,+A,+C", 0x7000003a, 0xfc00003f, WR_t|RD_s, 0, ICVM }, +{"exts32", "t,r,+A,+C", 0x7c00003b, 0xfc00003f, WR_t|RD_s, 0, ICVM }, +{"cins", "t,r,+A,+B", 0x70000032, 0xfc00003f, WR_t|RD_s, 0, ICVM }, +{"cins32", "t,r,+A,+B", 0x70000033, 0xfc00003f, WR_t|RD_s, 0, ICVM }, +{"mtm0", "s", 0x70000008, 0xfc1fffff, RD_s|WR_MPL0, 0, ICVM }, +{"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_s|WR_MPL1, 0, ICVM }, +{"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_s|WR_MPL2, 0, ICVM }, +{"mtp0", "s", 0x70000009, 0xfc1fffff, RD_s|WR_P0, 0, ICVM }, +{"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_s|WR_P1, 0, ICVM }, +{"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_s|WR_P2, 0, ICVM }, +{"dpop", "d,s", 0x7000002d, 0xfc1f07ff, RD_s|WR_d, 0, ICVM }, +{"pop", "d,s", 0x7000002c, 0xfc1f07ff, RD_s|WR_d, 0, ICVM }, /* Conflicts with the 4650's "mul" instruction. Nobody's using the 4010 any more, so move this insn out of the way. If the object format gave us more info, we could do this right. */ @@ -3603,6 +3650,12 @@ print_insn_args (const char *d, break; } + case 'p': + /* Cavium specific 5 bit value describing bit position. */ + (*info->fprintf_func) (info->stream, "0x%x", + (unsigned int)(l >> OP_SH_RT) & OP_MASK_RT); + break; + default: /* xgettext:c-format */ (*info->fprintf_func) (info->stream,