From patchwork Thu Aug 4 13:06:01 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Avi Kivity X-Patchwork-Id: 108447 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 60824B6F70 for ; Thu, 4 Aug 2011 23:08:41 +1000 (EST) Received: from localhost ([::1]:46874 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QoxfC-0003ct-7F for incoming@patchwork.ozlabs.org; Thu, 04 Aug 2011 09:08:38 -0400 Received: from eggs.gnu.org ([140.186.70.92]:45288) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QoxdW-0000tD-1g for qemu-devel@nongnu.org; Thu, 04 Aug 2011 09:07:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QoxdK-0007Mn-3t for qemu-devel@nongnu.org; Thu, 04 Aug 2011 09:06:53 -0400 Received: from mx1.redhat.com ([209.132.183.28]:10450) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QoxdJ-0007M0-SX for qemu-devel@nongnu.org; Thu, 04 Aug 2011 09:06:42 -0400 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p74D6ejQ003518 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 4 Aug 2011 09:06:40 -0400 Received: from cleopatra.tlv.redhat.com (cleopatra.tlv.redhat.com [10.35.255.11]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p74D6dXw003171; Thu, 4 Aug 2011 09:06:40 -0400 Received: from s01.tlv.redhat.com (s01.tlv.redhat.com [10.35.255.8]) by cleopatra.tlv.redhat.com (Postfix) with ESMTP id B3E6C250B3E; Thu, 4 Aug 2011 16:06:37 +0300 (IDT) From: Avi Kivity To: Anthony Liguori , qemu-devel@nongnu.org Date: Thu, 4 Aug 2011 16:06:01 +0300 Message-Id: <1312463195-13605-6-git-send-email-avi@redhat.com> In-Reply-To: <1312463195-13605-1-git-send-email-avi@redhat.com> References: <1312463195-13605-1-git-send-email-avi@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: kvm@vger.kernel.org, "Michael S. Tsirkin" Subject: [Qemu-devel] [PATCH v3 05/39] cirrus: simplify mmio BAR access functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Make use of the memory API's ability to satisfy multi-byte accesses via multiple single-byte accesses. Reviewed-by: Richard Henderson Signed-off-by: Avi Kivity --- hw/cirrus_vga.c | 78 +++++------------------------------------------------- 1 files changed, 8 insertions(+), 70 deletions(-) diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c index d1475dd..6e1aa75 100644 --- a/hw/cirrus_vga.c +++ b/hw/cirrus_vga.c @@ -2828,12 +2828,11 @@ static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) * ***************************************/ -static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) +static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr, + unsigned size) { CirrusVGAState *s = opaque; - addr &= CIRRUS_PNPMMIO_SIZE - 1; - if (addr >= 0x100) { return cirrus_mmio_blt_read(s, addr - 0x100); } else { @@ -2841,33 +2840,11 @@ static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) } } -static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr) -{ - uint32_t v; - - v = cirrus_mmio_readb(opaque, addr); - v |= cirrus_mmio_readb(opaque, addr + 1) << 8; - return v; -} - -static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr) -{ - uint32_t v; - - v = cirrus_mmio_readb(opaque, addr); - v |= cirrus_mmio_readb(opaque, addr + 1) << 8; - v |= cirrus_mmio_readb(opaque, addr + 2) << 16; - v |= cirrus_mmio_readb(opaque, addr + 3) << 24; - return v; -} - -static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, - uint32_t val) +static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size) { CirrusVGAState *s = opaque; - addr &= CIRRUS_PNPMMIO_SIZE - 1; - if (addr >= 0x100) { cirrus_mmio_blt_write(s, addr - 0x100, val); } else { @@ -2875,53 +2852,14 @@ static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, } } -static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr, - uint32_t val) -{ - cirrus_mmio_writeb(opaque, addr, val & 0xff); - cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); -} - -static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr, - uint32_t val) -{ - cirrus_mmio_writeb(opaque, addr, val & 0xff); - cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); - cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff); - cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff); -} - - -static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr, - unsigned size) -{ - CirrusVGAState *s = opaque; - - switch (size) { - case 1: return cirrus_mmio_readb(s, addr); - case 2: return cirrus_mmio_readw(s, addr); - case 4: return cirrus_mmio_readl(s, addr); - default: abort(); - } -}; - -static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr, - uint64_t data, unsigned size) -{ - CirrusVGAState *s = opaque; - - switch (size) { - case 1: return cirrus_mmio_writeb(s, addr, data); - case 2: return cirrus_mmio_writew(s, addr, data); - case 4: return cirrus_mmio_writel(s, addr, data); - default: abort(); - } -}; - static const MemoryRegionOps cirrus_mmio_io_ops = { .read = cirrus_mmio_read, .write = cirrus_mmio_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, }; /* load/save state */