From patchwork Thu Aug 4 13:06:28 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Avi Kivity X-Patchwork-Id: 108472 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BFC64B6F64 for ; Thu, 4 Aug 2011 23:53:08 +1000 (EST) Received: from localhost ([::1]:45146 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QoxeV-0002jN-EW for incoming@patchwork.ozlabs.org; Thu, 04 Aug 2011 09:07:55 -0400 Received: from eggs.gnu.org ([140.186.70.92]:45231) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QoxdT-0000i5-1D for qemu-devel@nongnu.org; Thu, 04 Aug 2011 09:06:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QoxdM-0007Qx-BD for qemu-devel@nongnu.org; Thu, 04 Aug 2011 09:06:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QoxdM-0007Pf-19 for qemu-devel@nongnu.org; Thu, 04 Aug 2011 09:06:44 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p74D6gFJ021912 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 4 Aug 2011 09:06:42 -0400 Received: from cleopatra.tlv.redhat.com (cleopatra.tlv.redhat.com [10.35.255.11]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p74D6fBP010420; Thu, 4 Aug 2011 09:06:42 -0400 Received: from s01.tlv.redhat.com (s01.tlv.redhat.com [10.35.255.8]) by cleopatra.tlv.redhat.com (Postfix) with ESMTP id 4A945250B59; Thu, 4 Aug 2011 16:06:38 +0300 (IDT) From: Avi Kivity To: Anthony Liguori , qemu-devel@nongnu.org Date: Thu, 4 Aug 2011 16:06:28 +0300 Message-Id: <1312463195-13605-33-git-send-email-avi@redhat.com> In-Reply-To: <1312463195-13605-1-git-send-email-avi@redhat.com> References: <1312463195-13605-1-git-send-email-avi@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: kvm@vger.kernel.org, "Michael S. Tsirkin" Subject: [Qemu-devel] [PATCH v3 32/39] xen-platform: convert to memory API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Since this device bypasses PCI and registers I/O ports directly with the system bus, it needs further attention. Reviewed-by: Richard Henderson Signed-off-by: Avi Kivity --- hw/xen_platform.c | 84 ++++++++++++++++++++++++++++++++--------------------- 1 files changed, 51 insertions(+), 33 deletions(-) diff --git a/hw/xen_platform.c b/hw/xen_platform.c index fb6be6a..239eefe 100644 --- a/hw/xen_platform.c +++ b/hw/xen_platform.c @@ -32,7 +32,6 @@ #include "xen_common.h" #include "net.h" #include "xen_backend.h" -#include "rwhandler.h" #include "trace.h" #include @@ -51,6 +50,9 @@ typedef struct PCIXenPlatformState { PCIDevice pci_dev; + MemoryRegion fixed_io; + MemoryRegion bar; + MemoryRegion mmio_bar; uint8_t flags; /* used only for version_id == 2 */ int drivers_blacklisted; uint16_t driver_product_version; @@ -221,21 +223,34 @@ static void platform_fixed_ioport_reset(void *opaque) platform_fixed_ioport_writeb(s, XEN_PLATFORM_IOPORT, 0); } +const MemoryRegionPortio xen_platform_ioport[] = { + { 0, 16, 4, .write = platform_fixed_ioport_writel, }, + { 0, 16, 2, .write = platform_fixed_ioport_writew, }, + { 0, 16, 1, .write = platform_fixed_ioport_writeb, }, + { 0, 16, 2, .read = platform_fixed_ioport_readw, }, + { 0, 16, 1, .read = platform_fixed_ioport_readb, }, + PORTIO_END +}; + +static const MemoryRegionOps platform_fixed_io_ops = { + .old_portio = xen_platform_ioport, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +#include "exec-memory.h" + static void platform_fixed_ioport_init(PCIXenPlatformState* s) { - register_ioport_write(XEN_PLATFORM_IOPORT, 16, 4, platform_fixed_ioport_writel, s); - register_ioport_write(XEN_PLATFORM_IOPORT, 16, 2, platform_fixed_ioport_writew, s); - register_ioport_write(XEN_PLATFORM_IOPORT, 16, 1, platform_fixed_ioport_writeb, s); - register_ioport_read(XEN_PLATFORM_IOPORT, 16, 2, platform_fixed_ioport_readw, s); - register_ioport_read(XEN_PLATFORM_IOPORT, 16, 1, platform_fixed_ioport_readb, s); + memory_region_init_io(&s->fixed_io, &platform_fixed_io_ops, s, + "xen-fixed", 16); + memory_region_add_subregion(get_system_io(), XEN_PLATFORM_IOPORT, + &s->fixed_io); } /* Xen Platform PCI Device */ static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr) { - addr &= 0xff; - if (addr == 0) { return platform_fixed_ioport_readb(opaque, XEN_PLATFORM_IOPORT); } else { @@ -247,9 +262,6 @@ static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val { PCIXenPlatformState *s = opaque; - addr &= 0xff; - val &= 0xff; - switch (addr) { case 0: /* Platform flags */ platform_fixed_ioport_writeb(opaque, XEN_PLATFORM_IOPORT, val); @@ -262,15 +274,23 @@ static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val } } -static void platform_ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr, pcibus_t size, int type) -{ - PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, pci_dev); +static MemoryRegionPortio xen_pci_portio[] = { + { 0, 0x100, 1, .read = xen_platform_ioport_readb, }, + { 0, 0x100, 1, .write = xen_platform_ioport_writeb, }, + PORTIO_END +}; + +static const MemoryRegionOps xen_pci_io_ops = { + .old_portio = xen_pci_portio, +}; - register_ioport_write(addr, size, 1, xen_platform_ioport_writeb, d); - register_ioport_read(addr, size, 1, xen_platform_ioport_readb, d); +static void platform_ioport_bar_setup(PCIXenPlatformState *d) +{ + memory_region_init_io(&d->bar, &xen_pci_io_ops, d, "xen-pci", 0x100); } -static uint32_t platform_mmio_read(ReadWriteHandler *handler, pcibus_t addr, int len) +static uint64_t platform_mmio_read(void *opaque, target_phys_addr_t addr, + unsigned size) { DPRINTF("Warning: attempted read from physical address " "0x" TARGET_FMT_plx " in xen platform mmio space\n", addr); @@ -278,28 +298,24 @@ static uint32_t platform_mmio_read(ReadWriteHandler *handler, pcibus_t addr, int return 0; } -static void platform_mmio_write(ReadWriteHandler *handler, pcibus_t addr, - uint32_t val, int len) +static void platform_mmio_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size) { - DPRINTF("Warning: attempted write of 0x%x to physical " + DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical " "address 0x" TARGET_FMT_plx " in xen platform mmio space\n", val, addr); } -static ReadWriteHandler platform_mmio_handler = { +static const MemoryRegionOps platform_mmio_handler = { .read = &platform_mmio_read, .write = &platform_mmio_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static void platform_mmio_map(PCIDevice *d, int region_num, - pcibus_t addr, pcibus_t size, int type) +static void platform_mmio_setup(PCIXenPlatformState *d) { - int mmio_io_addr; - - mmio_io_addr = cpu_register_io_memory_simple(&platform_mmio_handler, - DEVICE_NATIVE_ENDIAN); - - cpu_register_physical_memory(addr, size, mmio_io_addr); + memory_region_init_io(&d->mmio_bar, &platform_mmio_handler, d, + "xen-mmio", 0x1000000); } static int xen_platform_post_load(void *opaque, int version_id) @@ -337,12 +353,14 @@ static int xen_platform_initfn(PCIDevice *dev) pci_conf[PCI_INTERRUPT_PIN] = 1; - pci_register_bar(&d->pci_dev, 0, 0x100, - PCI_BASE_ADDRESS_SPACE_IO, platform_ioport_map); + platform_ioport_bar_setup(d); + pci_register_bar_region(&d->pci_dev, 0, + PCI_BASE_ADDRESS_SPACE_IO, &d->bar); /* reserve 16MB mmio address for share memory*/ - pci_register_bar(&d->pci_dev, 1, 0x1000000, - PCI_BASE_ADDRESS_MEM_PREFETCH, platform_mmio_map); + platform_mmio_setup(d); + pci_register_bar_region(&d->pci_dev, 1, + PCI_BASE_ADDRESS_MEM_PREFETCH, &d->mmio_bar); platform_fixed_ioport_init(d);