From patchwork Fri Jul 29 15:35:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 107426 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4A72BB6F57 for ; Sat, 30 Jul 2011 02:50:25 +1000 (EST) Received: from localhost ([::1]:33397 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qmp7Z-00031A-Ho for incoming@patchwork.ozlabs.org; Fri, 29 Jul 2011 11:37:05 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47932) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qmp6V-0000Q9-Cg for qemu-devel@nongnu.org; Fri, 29 Jul 2011 11:36:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qmp6P-00027j-0T for qemu-devel@nongnu.org; Fri, 29 Jul 2011 11:35:53 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:36200) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qmp6O-0001zI-L1 for qemu-devel@nongnu.org; Fri, 29 Jul 2011 11:35:52 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Qmp60-0007Zv-9A; Fri, 29 Jul 2011 16:35:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org, Anthony Liguori Date: Fri, 29 Jul 2011 16:35:25 +0100 Message-Id: <1311953728-29084-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1311953728-29084-1-git-send-email-peter.maydell@linaro.org> References: <1311953728-29084-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Subject: [Qemu-devel] [PATCH 12/15] onenand: Pass BlockDriverState to init function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Pass the BlockDriverState to the onenand init function so it doesn't need to look up the drive itself. Signed-off-by: Peter Maydell --- hw/flash.h | 3 ++- hw/nseries.c | 10 ++++++---- hw/onenand.c | 14 ++++++++------ 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/hw/flash.h b/hw/flash.h index 43260ce..1aae43d 100644 --- a/hw/flash.h +++ b/hw/flash.h @@ -38,7 +38,8 @@ uint32_t nand_getbuswidth(DeviceState *dev); /* onenand.c */ void onenand_base_update(void *opaque, target_phys_addr_t new); void onenand_base_unmap(void *opaque); -void *onenand_init(uint32_t id, int regshift, qemu_irq irq); +void *onenand_init(BlockDriverState *bdrv, uint32_t id, + int regshift, qemu_irq irq); void *onenand_raw_otp(void *opaque); /* ecc.c */ diff --git a/hw/nseries.c b/hw/nseries.c index 45b52bb..96cc490 100644 --- a/hw/nseries.c +++ b/hw/nseries.c @@ -31,6 +31,7 @@ #include "hw.h" #include "bt.h" #include "loader.h" +#include "blockdev.h" /* Nokia N8x0 support */ struct n800_s { @@ -163,13 +164,14 @@ static const uint8_t n8x0_cal_bt_id[] = { static void n8x0_nand_setup(struct n800_s *s) { char *otp_region; + DriveInfo *dinfo; + dinfo = drive_get(IF_MTD, 0, 0); /* Either ec40xx or ec48xx are OK for the ID */ + s->nand = onenand_init(dinfo ? dinfo->bdrv : 0, 0xec4800, 1, + qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO)); omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update, - onenand_base_unmap, - (s->nand = onenand_init(0xec4800, 1, - qdev_get_gpio_in(s->cpu->gpio, - N8X0_ONENAND_GPIO)))); + onenand_base_unmap, s->nand); otp_region = onenand_raw_otp(s->nand); memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac)); diff --git a/hw/onenand.c b/hw/onenand.c index 71c1ab4..3a19d7f 100644 --- a/hw/onenand.c +++ b/hw/onenand.c @@ -615,10 +615,10 @@ static CPUWriteMemoryFunc * const onenand_writefn[] = { onenand_write, }; -void *onenand_init(uint32_t id, int regshift, qemu_irq irq) +void *onenand_init(BlockDriverState *bdrv, uint32_t id, + int regshift, qemu_irq irq) { OneNANDState *s = (OneNANDState *) qemu_mallocz(sizeof(*s)); - DriveInfo *dinfo = drive_get(IF_MTD, 0, 0); uint32_t size = 1 << (24 + ((id >> 12) & 7)); void *ram; @@ -632,11 +632,13 @@ void *onenand_init(uint32_t id, int regshift, qemu_irq irq) s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0; s->iomemtype = cpu_register_io_memory(onenand_readfn, onenand_writefn, s, DEVICE_NATIVE_ENDIAN); - if (!dinfo) + s->bdrv = bdrv; + if (!s->bdrv) { s->image = memset(qemu_malloc(size + (size >> 5)), - 0xff, size + (size >> 5)); - else - s->bdrv = dinfo->bdrv; + 0xff, size + (size >> 5)); + } else { + s->bdrv_cur = s->bdrv; + } s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT), 0xff, (64 + 2) << PAGE_SHIFT); s->ram = qemu_ram_alloc(NULL, "onenand.ram", 0xc000 << s->shift);