Message ID | 1306997503-29304-14-git-send-email-agraf@suse.de |
---|---|
State | New |
Headers | show |
diff --git a/target-s390x/translate.c b/target-s390x/translate.c index afeb5e6..eda4624 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -3473,6 +3473,9 @@ static void disas_b9(DisasContext *s, int op, int r1, int r2) tcg_temp_free_i64(tmp2); tcg_temp_free_i64(tmp3); break; + case 0x0f: /* LRVGR R1,R2 [RRE] */ + tcg_gen_bswap64_i64(regs[r1], regs[r2]); + break; case 0x1f: /* LRVR R1,R2 [RRE] */ tmp32_1 = load_reg32(r2); tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
The LRVGR instruction was missing. Implement it, so everyone's happy. Reported-by: Balazs Kutil <bkutil@novell.com> Signed-off-by: Alexander Graf <agraf@suse.de> --- target-s390x/translate.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)