From patchwork Mon May 23 20:28:46 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 97058 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3FD44B6FB9 for ; Tue, 24 May 2011 06:38:54 +1000 (EST) Received: from localhost ([::1]:54907 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObtr-0004C8-BG for incoming@patchwork.ozlabs.org; Mon, 23 May 2011 16:38:51 -0400 Received: from eggs.gnu.org ([140.186.70.92]:42953) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObks-0005gO-11 for qemu-devel@nongnu.org; Mon, 23 May 2011 16:29:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QObkr-0008Pn-4z for qemu-devel@nongnu.org; Mon, 23 May 2011 16:29:33 -0400 Received: from mail-gx0-f173.google.com ([209.85.161.173]:34382) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObkr-0008Gg-2R for qemu-devel@nongnu.org; Mon, 23 May 2011 16:29:33 -0400 Received: by mail-gx0-f173.google.com with SMTP id 26so2727982gxk.4 for ; Mon, 23 May 2011 13:29:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=AYix2ZfkerbNjcgxzeGQIm+pKIbZyazRjstpAnBfwZM=; b=XR7ZkrCzo28rfp1WH8dsSod6YDtQXA+bt0j6DiMyPJecVQ/4mxpckaAKwLtrpd5dpL 7GEhtq3JKmXu7uIyomdYYXovcm5WIKFbtlD+G/3lw7yilRfn8LBBWOLeuMjER17+SXRd tQR4Kdq2b3MUW/e2J8kCLt8Kzu9wfvU3IoeBI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=wHEKuApBLI3L61FTxKWfypJ5IjzCJpbCZTnmfD6xkpcBl2Cfqo/ScQp0mv8qvs5KE9 3U8CP8Nby7da5UPag0ENWrZYYWjnnwB36cMEGd3PLp1/09JAE/ZeDP8aawdqWkPwavfx EP67+zL/ZjYfPukqM5GCW3bPCO5myoHGzYSxo= Received: by 10.146.115.1 with SMTP id n1mr2563795yac.12.1306182572697; Mon, 23 May 2011 13:29:32 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net [71.227.161.214]) by mx.google.com with ESMTPS id e9sm5033668ann.24.2011.05.23.13.29.31 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 23 May 2011 13:29:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 23 May 2011 13:28:46 -0700 Message-Id: <1306182526-12081-27-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1306182526-12081-1-git-send-email-rth@twiddle.net> References: <1306182526-12081-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.161.173 Subject: [Qemu-devel] [PATCH 26/26] target-alpha: Implement TLB flush primitives. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Expose these via MTPR, more or less like the real HW does. Signed-off-by: Richard Henderson --- target-alpha/helper.h | 3 +++ target-alpha/op_helper.c | 11 ++++++++++- target-alpha/translate.c | 32 +++++++++++++++++++++----------- 3 files changed, 34 insertions(+), 12 deletions(-) diff --git a/target-alpha/helper.h b/target-alpha/helper.h index 9ffc372..2dec57e 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -110,6 +110,9 @@ DEF_HELPER_2(stl_phys, void, i64, i64) DEF_HELPER_2(stq_phys, void, i64, i64) DEF_HELPER_2(stl_c_phys, i64, i64, i64) DEF_HELPER_2(stq_c_phys, i64, i64, i64) + +DEF_HELPER_FLAGS_0(tbia, TCG_CALL_CONST, void) +DEF_HELPER_FLAGS_1(tbis, TCG_CALL_CONST, void, i64) #endif #include "def-helper.h" diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index 36b8289..d332719 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1205,6 +1205,16 @@ void helper_hw_ret (uint64_t a) swap_shadow_regs(env); } } + +void helper_tbia(void) +{ + tlb_flush(env, 1); +} + +void helper_tbis(uint64_t p) +{ + tlb_flush_page(env, p); +} #endif /*****************************************************************************/ @@ -1335,5 +1345,4 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) } env = saved_env; } - #endif diff --git a/target-alpha/translate.c b/target-alpha/translate.c index e664d62..ad6c2ca 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1621,7 +1621,6 @@ static void gen_mfpr(int ra, int regno) static void gen_mtpr(int rb, int regno) { TCGv tmp; - int data; if (rb == 31) { tmp = tcg_const_i64(0); @@ -1629,16 +1628,27 @@ static void gen_mtpr(int rb, int regno) tmp = cpu_ir[rb]; } - /* The basic registers are data only, and unknown registers - are read-zero, write-ignore. */ - data = cpu_pr_data(regno); - if (data != 0) { - if (data & PR_BYTE) { - tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); - } else if (data & PR_LONG) { - tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); - } else { - tcg_gen_st_i64(tmp, cpu_env, data); + /* These two register numbers perform a TLB cache flush. Thankfully we + can only do this inside PALmode, which means that the current basic + block cannot be affected by the change in mappings. */ + if (regno == 255) { + /* TBIA */ + gen_helper_tbia(); + } else if (regno == 254) { + /* TBIS */ + gen_helper_tbis(tmp); + } else { + /* The basic registers are data only, and unknown registers + are read-zero, write-ignore. */ + int data = cpu_pr_data(regno); + if (data != 0) { + if (data & PR_BYTE) { + tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); + } else if (data & PR_LONG) { + tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); + } else { + tcg_gen_st_i64(tmp, cpu_env, data); + } } }