From patchwork Tue May 17 22:32:46 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 96070 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9DFC5B6EE6 for ; Wed, 18 May 2011 08:39:46 +1000 (EST) Received: from localhost ([::1]:57314 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMSvY-0007oF-0x for incoming@patchwork.ozlabs.org; Tue, 17 May 2011 18:39:44 -0400 Received: from eggs.gnu.org ([140.186.70.92]:50796) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMSqM-0007VH-Fd for qemu-devel@nongnu.org; Tue, 17 May 2011 18:34:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QMSqL-0000UA-CT for qemu-devel@nongnu.org; Tue, 17 May 2011 18:34:22 -0400 Received: from mail-ew0-f45.google.com ([209.85.215.45]:37210) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMSqL-0000KZ-86 for qemu-devel@nongnu.org; Tue, 17 May 2011 18:34:21 -0400 Received: by mail-ew0-f45.google.com with SMTP id 24so340090ewy.4 for ; Tue, 17 May 2011 15:34:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=SAtgusrZzFcoNfs5LZUHM9cVM9FwH+MaF1XMm5YchDY=; b=vWg+cuXfctHJgmK1eD1s7MyplXRpTwMB+yNsm6nlEeKHRvDlbpfMFdrT4xt8V7+gyF M9b0K8UwwKbc6Oanhg/Z3mtcxRjX/Nd6OG+6YBKbJBDDX70pcUjDMEK51LaGws2kZMaS Yf2XnDIeaViKHYXr1BJ3STvuqJeACapK6WUE8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=ZV2KLXn58Wr5qh708VEAnnOG2x8XCsA6vTcMkmSe19RS+DW3Hd5DgZc1jfTFy/3wZY Jtes1BvWyPDDA+5KsIj7pg6/7ZIu9jy4d28zatdgigS5PyQ9MQSXNXSrJZvbuuNOYvDi UwUrVB62TBbjybwXWKBUIjeWI+A6Bt+0bGU3o= Received: by 10.14.9.231 with SMTP id 79mr386193eet.241.1305671660892; Tue, 17 May 2011 15:34:20 -0700 (PDT) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id y18sm692235eeh.24.2011.05.17.15.34.18 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 17 May 2011 15:34:20 -0700 (PDT) Received: by octofox.metropolis (sSMTP sendmail emulation); Wed, 18 May 2011 02:34:17 +0400 From: Max Filippov To: qemu-devel@nongnu.org Date: Wed, 18 May 2011 02:32:46 +0400 Message-Id: <1305671572-5899-21-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1305671572-5899-1-git-send-email-jcmvbkbc@gmail.com> References: <1305671572-5899-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.215.45 Cc: Max Filippov Subject: [Qemu-devel] [PATCH 20/26] target-xtensa: implement extended L32R X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org See ISA, 4.3.3 for details. TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR. Signed-off-by: Max Filippov --- RFC -> PATCH changes: - add XTENSA_TBFLAG_LITBASE, use it in L32R; --- target-xtensa/cpu.h | 6 ++++++ target-xtensa/helper.c | 1 + target-xtensa/translate.c | 19 +++++++++++++++---- 3 files changed, 22 insertions(+), 4 deletions(-) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 026b854..793a6b5 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -110,6 +110,7 @@ enum { LEND = 1, LCOUNT = 2, SAR = 3, + LITBASE = 5, SCOMPARE1 = 12, WINDOW_BASE = 72, WINDOW_START = 73, @@ -261,6 +262,7 @@ static inline int cpu_mmu_index(CPUState *env) } #define XTENSA_TBFLAG_EXCM 0x1 +#define XTENSA_TBFLAG_LITBASE 0x2 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, target_ulong *cs_base, int *flags) @@ -271,6 +273,10 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, if (env->sregs[PS] & PS_EXCM) { *flags |= XTENSA_TBFLAG_EXCM; } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && + (env->sregs[LITBASE] & 1)) { + *flags |= XTENSA_TBFLAG_LITBASE; + } } #include "cpu-all.h" diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 0eb3b9a..ffa5590 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -38,6 +38,7 @@ void cpu_reset(CPUXtensaState *env) { env->exception_taken = 0; env->pc = env->config->exception_vector[EXC_RESET]; + env->sregs[LITBASE] &= ~1; env->sregs[PS] = 0x1f; } diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index e5e4ce7..592072a 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -47,6 +47,7 @@ typedef struct DisasContext { uint32_t next_pc; int mem_idx; uint32_t lend; + uint32_t litbase; int is_jmp; int singlestep_enabled; @@ -69,6 +70,7 @@ static const char * const sregnames[256] = { [LEND] = "LEND", [LCOUNT] = "LCOUNT", [SAR] = "SAR", + [LITBASE] = "LITBASE", [SCOMPARE1] = "SCOMPARE1", [WINDOW_BASE] = "WINDOW_BASE", [WINDOW_START] = "WINDOW_START", @@ -314,6 +316,13 @@ static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s) dc->sar_m32_5bit = false; } +static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) +{ + tcg_gen_mov_i32(cpu_SR[sr], s); + /* This can change tb->flags, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); +} + static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) { gen_helper_wsr_windowbase(v); @@ -325,6 +334,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) uint32_t sr, TCGv_i32 v) = { [LEND] = gen_wsr_lend, [SAR] = gen_wsr_sar, + [LITBASE] = gen_wsr_litbase, [WINDOW_BASE] = gen_wsr_windowbase, }; @@ -1250,10 +1260,10 @@ static void disas_xtensa_insn(DisasContext *dc) case 1: /*L32R*/ { TCGv_i32 tmp = tcg_const_i32( - (0xfffc0000 | (RI16_IMM16 << 2)) + - ((dc->pc + 3) & ~3)); - - /* no ext L32R */ + ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ? + dc->litbase : + ((dc->pc + 3) & ~3)) + + (0xfffc0000 | (RI16_IMM16 << 2))); tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, 0); tcg_temp_free(tmp); @@ -1780,6 +1790,7 @@ static void gen_intermediate_code_internal( dc.pc = env->pc; dc.mem_idx = cpu_mmu_index(env); dc.lend = env->sregs[LEND]; + dc.litbase = env->sregs[LITBASE] & 0xfffff000; dc.is_jmp = DISAS_NEXT; reset_sar_tracker(&dc);