From patchwork Wed May 4 20:34:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 94142 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5C7571007DB for ; Thu, 5 May 2011 06:37:18 +1000 (EST) Received: from localhost ([::1]:38978 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHiot-000504-MZ for incoming@patchwork.ozlabs.org; Wed, 04 May 2011 16:37:15 -0400 Received: from eggs.gnu.org ([140.186.70.92]:56301) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHimQ-0000sw-LL for qemu-devel@nongnu.org; Wed, 04 May 2011 16:34:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QHimP-00028r-MN for qemu-devel@nongnu.org; Wed, 04 May 2011 16:34:42 -0400 Received: from mail-pv0-f173.google.com ([74.125.83.173]:41834) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHimP-00028e-Fy for qemu-devel@nongnu.org; Wed, 04 May 2011 16:34:41 -0400 Received: by pvg3 with SMTP id 3so812010pvg.4 for ; Wed, 04 May 2011 13:34:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:cc:subject:date:message-id :x-mailer:in-reply-to:references; bh=qbDOImAp8XGKEJdKxDo5lpdx0vb0YsFlrqmdLpCUWGw=; b=PWTARw6ly30o02puYZBDDqXM8aIoUj24Vl25LCtTTfYyueogPOIb1NMumOBEqNgdn+ XMHy7JhHi3gi55wWGXYtCdX6BW8G02yb6wEqdGh82cI+wv2hcxd0fiashrwMioWjUXDm VJLR1IxLH1VF35+jHsGkpTIOvH5y4tR80i1QM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; b=CrXbxLwir99QwHpPsrGdq67Jo9zIjYHs1rjADa/6t1EKxEKxKgsi9BX8D4i6AI33HA TpcJOSIdgImFjpJkHYlQ1BAiJm6W8THeuZRDSKmTNrsrQNfqvvAubJRSUPSKGwP89tuL zLBYjZWpDpBKyR/kl10/PYmihOlW1TYYsxCSQ= Received: by 10.68.38.163 with SMTP id h3mr2135829pbk.196.1304541280786; Wed, 04 May 2011 13:34:40 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id q19sm939433pbt.88.2011.05.04.13.34.39 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 May 2011 13:34:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 May 2011 13:34:25 -0700 Message-Id: <1304541271-5891-3-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304541271-5891-1-git-send-email-rth@twiddle.net> References: <1304541271-5891-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.83.173 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 2/8] irq: Introduce and use CPU_INTERRUPT_SSTEP_MASK. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This mask contains all of the bits that should be ignored while single stepping in the debugger. The mask contains 2 bits that are not currently cleared, but are also never set. The bits are included in the mask for consistency in handling of the CPU_INTERRUPT_TGT_EXT_N bits. Signed-off-by: Richard Henderson --- cpu-all.h | 8 ++++++++ cpu-exec.c | 5 +---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index dd9c230..bc0dad8 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -837,6 +837,14 @@ extern CPUState *cpu_single_env; #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 +/* The set of all bits that should be masked when single-stepping. */ +#define CPU_INTERRUPT_SSTEP_MASK \ + (CPU_INTERRUPT_HARD \ + | CPU_INTERRUPT_TGT_EXT_0 \ + | CPU_INTERRUPT_TGT_EXT_1 \ + | CPU_INTERRUPT_TGT_EXT_2 \ + | CPU_INTERRUPT_TGT_EXT_3 \ + | CPU_INTERRUPT_TGT_EXT_4) #ifndef CONFIG_USER_ONLY typedef void (*CPUInterruptHandler)(CPUState *, int); diff --git a/cpu-exec.c b/cpu-exec.c index 395cd8c..5b42b25 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -360,10 +360,7 @@ int cpu_exec(CPUState *env1) if (unlikely(interrupt_request)) { if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) { /* Mask out external interrupts for this step. */ - interrupt_request &= ~(CPU_INTERRUPT_HARD | - CPU_INTERRUPT_FIQ | - CPU_INTERRUPT_SMI | - CPU_INTERRUPT_NMI); + interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK; } if (interrupt_request & CPU_INTERRUPT_DEBUG) { env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;