From patchwork Sat Apr 30 22:24:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 93528 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B3A6BB6F5B for ; Sun, 1 May 2011 08:26:04 +1000 (EST) Received: from localhost ([::1]:57253 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QGIby-0001Hp-2Y for incoming@patchwork.ozlabs.org; Sat, 30 Apr 2011 18:26:02 -0400 Received: from eggs.gnu.org ([140.186.70.92]:49124) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QGIag-0007lS-PW for qemu-devel@nongnu.org; Sat, 30 Apr 2011 18:24:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QGIaf-0004hX-W6 for qemu-devel@nongnu.org; Sat, 30 Apr 2011 18:24:42 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:42205) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QGIaf-0004hP-PB for qemu-devel@nongnu.org; Sat, 30 Apr 2011 18:24:41 -0400 Received: by pzk30 with SMTP id 30so3274281pzk.4 for ; Sat, 30 Apr 2011 15:24:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:cc:subject:date:message-id :x-mailer:in-reply-to:references; bh=Wx9MViAlx/tRQ3MLRrA2Oag3LyCOoVHL1StIVh0ED9U=; b=rlCHZWxnHe6FCH6RDgo+FLu1Ty2HVlu6CQMaVLthovHV9LfqWLI2pYMCChG+4ReMTi 9SHVMTTjNzyoXZnPn/MwtEB7R4Fu/3AORnY8FiahOKWvsTMyTF3K9P6B6VQXKvi0CxXw I4ei2Llxl/IPngqEKVGMiYq4K9xeno5UAV6nE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; b=K8t+Uy0fcWiY7EVWQWqGeQV4Su06lgRElfHawqbTkaIJug8KuOOTh0T1yCko3QVb71 P/UbfkiQ7eahZzEAMD6UPlQKK2HDbs/xhF+LlxBEFJRfJpwvKYXL4jKAdBu8jOc+pLPV USahXTK4TWFJ/xFRTqhnKGEu+t+aY/2T245Cs= Received: by 10.68.17.35 with SMTP id l3mr6767687pbd.523.1304202280921; Sat, 30 Apr 2011 15:24:40 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id y7sm2797195pbk.30.2011.04.30.15.24.39 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 30 Apr 2011 15:24:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 30 Apr 2011 15:24:25 -0700 Message-Id: <1304202271-24730-3-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304202271-24730-1-git-send-email-rth@twiddle.net> References: <1304202271-24730-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.210.45 Cc: Blue Swirl , Aurelien Jarno Subject: [Qemu-devel] [PATCH 2/8] irq: Introduce and use CPU_INTERRUPT_SSTEP_MASK. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This mask contains all of the bits that should be ignored while single stepping in the debugger. The mask contains 2 bits that are not currently cleared, but are also never set. The bits are included in the mask for consistency in handling of the CPU_INTERRUPT_TGT_EXT_N bits. Signed-off-by: Richard Henderson --- cpu-all.h | 8 ++++++++ cpu-exec.c | 5 +---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index 8c3222e..f813ef8 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -837,6 +837,14 @@ extern CPUState *cpu_single_env; #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 +/* The set of all bits that should be masked when single-stepping. */ +#define CPU_INTERRUPT_SSTEP_MASK \ + (CPU_INTERRUPT_HARD \ + | CPU_INTERRUPT_TGT_EXT_0 \ + | CPU_INTERRUPT_TGT_EXT_1 \ + | CPU_INTERRUPT_TGT_EXT_2 \ + | CPU_INTERRUPT_TGT_EXT_3 \ + | CPU_INTERRUPT_TGT_EXT_4) void cpu_interrupt(CPUState *s, int mask); void cpu_reset_interrupt(CPUState *env, int mask); diff --git a/cpu-exec.c b/cpu-exec.c index 395cd8c..5b42b25 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -360,10 +360,7 @@ int cpu_exec(CPUState *env1) if (unlikely(interrupt_request)) { if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) { /* Mask out external interrupts for this step. */ - interrupt_request &= ~(CPU_INTERRUPT_HARD | - CPU_INTERRUPT_FIQ | - CPU_INTERRUPT_SMI | - CPU_INTERRUPT_NMI); + interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK; } if (interrupt_request & CPU_INTERRUPT_DEBUG) { env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;