From patchwork Thu Apr 28 20:50:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 93306 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C78A31007DB for ; Fri, 29 Apr 2011 06:54:55 +1000 (EST) Received: from localhost ([::1]:36843 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYEd-0002TF-2D for incoming@patchwork.ozlabs.org; Thu, 28 Apr 2011 16:54:51 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47880) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBc-0005Nf-Nx for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QFYBb-0005da-9B for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:44 -0400 Received: from mail-px0-f179.google.com ([209.85.212.179]:45275) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBb-0005Xx-0g for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:43 -0400 Received: by mail-px0-f179.google.com with SMTP id 2so298075pxi.10 for ; Thu, 28 Apr 2011 13:51:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=hxfiT4X8Hjp1C0do5WOtkXE8tpmM5vD6AHiHac1pptg=; b=oD8TXrV/st4p6E8tHxozneeyrXgvXwlNSy86aAQ51iyHN8vLgHkUvAnbNJcBv2Dzh9 u9EAZwalsf4tWvVWaNDDzCTCMkF6IPDFWi13IHYwmY4fVW40fIgto5ne2y1Z5ZZYuJcf GPzl/kbXdJ3L/nEjO6xvw6dNz58WwsPFE1ooA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=JcBqL9RoXTRJ01CAjZQMOoZjoNKPqkNNyKFPv16dTiUnp1if7sbjqHTqbZc0soU8+u 5YVsa7aIQUpyeUFj3aKK98NeM6C6PSAWZ6RJtVJ4hM9pensmgaaLgkgqFjH5dw3RB9um CimYo/Dlu6sEL4UyDo+9mbORwdKGTUV36+5ow= Received: by 10.142.224.17 with SMTP id w17mr1398269wfg.63.1304023902452; Thu, 28 Apr 2011 13:51:42 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id z10sm2266797wfj.12.2011.04.28.13.51.41 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Apr 2011 13:51:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Apr 2011 13:50:58 -0700 Message-Id: <1304023875-25040-17-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304023875-25040-1-git-send-email-rth@twiddle.net> References: <1304023875-25040-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.212.179 Subject: [Qemu-devel] [PATCH 16/33] target-alpha: Implement do_interrupt for system mode. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-alpha/helper.c | 121 +++++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 111 insertions(+), 10 deletions(-) diff --git a/target-alpha/helper.c b/target-alpha/helper.c index c5479fd..a49f632 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -160,7 +160,6 @@ void cpu_alpha_store_fpcr (CPUState *env, uint64_t val) } #if defined(CONFIG_USER_ONLY) - int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int mmu_idx, int is_softmmu) { @@ -168,14 +167,7 @@ int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw, env->trap_arg0 = address; return 1; } - -void do_interrupt (CPUState *env) -{ - env->exception_index = -1; -} - #else - target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) { return -1; @@ -186,12 +178,121 @@ int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw, { return 0; } +#endif /* USER_ONLY */ void do_interrupt (CPUState *env) { - abort(); + int i = env->exception_index; + + if (qemu_loglevel_mask(CPU_LOG_INT)) { + static int count; + const char *name = ""; + + switch (i) { + case EXCP_RESET: + name = "reset"; + break; + case EXCP_MCHK: + name = "mchk"; + break; + case EXCP_SMP_INTERRUPT: + name = "smp_interrupt"; + break; + case EXCP_CLK_INTERRUPT: + name = "clk_interrupt"; + break; + case EXCP_DEV_INTERRUPT: + name = "dev_interrupt"; + break; + case EXCP_MMFAULT: + name = "mmfault"; + break; + case EXCP_UNALIGN: + name = "unalign"; + break; + case EXCP_OPCDEC: + name = "opcdec"; + break; + case EXCP_ARITH: + name = "arith"; + break; + case EXCP_FEN: + name = "fen"; + break; + case EXCP_CALL_PAL: + name = "call_pal"; + break; + case EXCP_STL_C: + name = "stl_c"; + break; + case EXCP_STQ_C: + name = "stq_c"; + break; + } + qemu_log("INT %6d: %s(%#x) pc=%016" PRIx64 " sp=%016" PRIx64 "\n", + ++count, name, env->error_code, env->pc, env->ir[IR_SP]); + } + + env->exception_index = -1; + +#if !defined(CONFIG_USER_ONLY) + switch (i) { + case EXCP_RESET: + i = 0x0000; + break; + case EXCP_MCHK: + i = 0x0080; + break; + case EXCP_SMP_INTERRUPT: + i = 0x0100; + break; + case EXCP_CLK_INTERRUPT: + i = 0x0180; + break; + case EXCP_DEV_INTERRUPT: + i = 0x0200; + break; + case EXCP_MMFAULT: + i = 0x0280; + break; + case EXCP_UNALIGN: + i = 0x0300; + break; + case EXCP_OPCDEC: + i = 0x0380; + break; + case EXCP_ARITH: + i = 0x0400; + break; + case EXCP_FEN: + i = 0x0480; + break; + case EXCP_CALL_PAL: + i = env->error_code; + /* There are 64 entry points for both privilaged and unprivlaged, + with bit 0x80 indicating unprivlaged. Each entry point gets + 64 bytes to do its job. */ + if (i & 0x80) { + i = 0x2000 + (i - 0x80) * 64; + } else { + i = 0x1000 + i * 64; + } + break; + default: + cpu_abort(env, "Unhandled CPU exception"); + } + + /* Remember where the exception happened. Emulate real hardware in + that the low bit of the PC indicates PALmode. */ + env->exc_addr = env->pc | env->pal_mode; + + /* Continue execution at the PALcode entry point. */ + env->pc = env->palbr + i; + + /* Switch to PALmode. */ + env->pal_mode = 1; +#endif /* !USER_ONLY */ } -#endif void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf, int flags)