From patchwork Tue Apr 19 15:04:51 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 92007 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E4802B6FE1 for ; Wed, 20 Apr 2011 01:45:44 +1000 (EST) Received: from localhost ([::1]:55530 helo=lists2.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QCD7W-0000tU-A3 for incoming@patchwork.ozlabs.org; Tue, 19 Apr 2011 11:45:42 -0400 Received: from eggs.gnu.org ([140.186.70.92]:53949) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QCD6P-0007mZ-Gi for qemu-devel@nongnu.org; Tue, 19 Apr 2011 11:44:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QCD6N-0005um-NC for qemu-devel@nongnu.org; Tue, 19 Apr 2011 11:44:33 -0400 Received: from a.mail.sonic.net ([64.142.16.245]:56651) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QCD6N-0005uX-Ft for qemu-devel@nongnu.org; Tue, 19 Apr 2011 11:44:31 -0400 Received: from are.twiddle.net (are.twiddle.net [75.101.38.216]) by a.mail.sonic.net (8.13.8.Beta0-Sonic/8.13.7) with ESMTP id p3JF57Mi030848 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 19 Apr 2011 08:05:07 -0700 Received: from are.twiddle.net (localhost [127.0.0.1]) by are.twiddle.net (8.14.4/8.14.4) with ESMTP id p3JF57sN012868 for ; Tue, 19 Apr 2011 08:05:07 -0700 Received: (from rth@localhost) by are.twiddle.net (8.14.4/8.14.4/Submit) id p3JF57xo012867 for qemu-devel@nongnu.org; Tue, 19 Apr 2011 08:05:07 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Apr 2011 08:04:51 -0700 Message-Id: <1303225501-12778-15-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1303225501-12778-1-git-send-email-rth@twiddle.net> References: <1303225501-12778-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 64.142.16.245 Subject: [Qemu-devel] [PATCH 14/24] target-alpha: Add various symbolic constants. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The EXC_M_* constants were being set for the EV6, not as set for the Unix kernel entry point. Use PS_USER_MODE instead of hard-coding access to the PS register. Signed-off-by: Richard Henderson --- target-alpha/cpu.h | 56 +++++++++++++++++++++++++++++++++++---------- target-alpha/translate.c | 2 +- 2 files changed, 44 insertions(+), 14 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index f6549f9..d8f2514 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -290,11 +290,6 @@ struct CPUAlphaState { #define cpu_gen_code cpu_alpha_gen_code #define cpu_signal_handler cpu_alpha_signal_handler -static inline int cpu_mmu_index (CPUState *env) -{ - return (env->ps >> 3) & 1; -} - #include "cpu-all.h" enum { @@ -320,14 +315,49 @@ enum { EXCP_STQ_C, }; -/* Arithmetic exception */ -#define EXC_M_IOV (1<<16) /* Integer Overflow */ -#define EXC_M_INE (1<<15) /* Inexact result */ -#define EXC_M_UNF (1<<14) /* Underflow */ -#define EXC_M_FOV (1<<13) /* Overflow */ -#define EXC_M_DZE (1<<12) /* Division by zero */ -#define EXC_M_INV (1<<11) /* Invalid operation */ -#define EXC_M_SWC (1<<10) /* Software completion */ +/* Hardware interrupt (entInt) constants. */ +enum { + INT_K_IP, + INT_K_CLK, + INT_K_MCHK, + INT_K_DEV, + INT_K_PERF, +}; + +/* Memory management (entMM) constants. */ +enum { + MM_K_TNV, + MM_K_ACV, + MM_K_FOR, + MM_K_FOE, + MM_K_FOW +}; + +/* Arithmetic exception (entArith) constants. */ +enum { + EXC_M_SWC = 1, /* Software completion */ + EXC_M_INV = 2, /* Invalid operation */ + EXC_M_DZE = 4, /* Division by zero */ + EXC_M_FOV = 8, /* Overflow */ + EXC_M_UNF = 16, /* Underflow */ + EXC_M_INE = 32, /* Inexact result */ + EXC_M_IOV = 64 /* Integer Overflow */ +}; + +/* Processor status constants. */ +enum { + /* Low 3 bits are interrupt mask level. */ + PS_INT_MASK = 7, + + /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes; + The Unix PALcode only uses bit 4. */ + PS_USER_MODE = 8 +}; + +static inline int cpu_mmu_index (CPUState *env) +{ + return (env->ps & PS_USER_MODE) != 0; +} enum { IR_V0 = 0, diff --git a/target-alpha/translate.c b/target-alpha/translate.c index c8ef31d..2c622b9 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3354,7 +3354,7 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model) env->amask = amask; #if defined (CONFIG_USER_ONLY) - env->ps = 1 << 3; + env->ps = PS_USER_MODE; cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD | FPCR_UNFD | FPCR_INED | FPCR_DNOD)); #else