From patchwork Fri Apr 1 14:30:42 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 89263 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CA0ECB6F94 for ; Sat, 2 Apr 2011 01:32:36 +1100 (EST) Received: from localhost ([127.0.0.1]:47702 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Q5fOq-0002jm-6u for incoming@patchwork.ozlabs.org; Fri, 01 Apr 2011 10:32:32 -0400 Received: from [140.186.70.92] (port=57115 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Q5fNG-0002jC-AC for qemu-devel@nongnu.org; Fri, 01 Apr 2011 10:30:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Q5fNE-0004rg-Mr for qemu-devel@nongnu.org; Fri, 01 Apr 2011 10:30:54 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:45963) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Q5fNE-0004or-88 for qemu-devel@nongnu.org; Fri, 01 Apr 2011 10:30:52 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Q5fN5-0007ml-B8; Fri, 01 Apr 2011 15:30:43 +0100 From: Peter Maydell To: Anthony Liguori , qemu-devel@nongnu.org Date: Fri, 1 Apr 2011 15:30:42 +0100 Message-Id: <1301668243-29886-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1301668243-29886-1-git-send-email-peter.maydell@linaro.org> References: <1301668243-29886-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 09/10] target-arm: Don't leak TCG temp for UNDEFs in Neon load/store space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Move the allocation and freeing of the TCG temp used for the address for Neon load/store instructions so that we don't allocate the temporary until we've done enough decoding to know that the instruction is not an UNDEF pattern; this avoids leaking the TCG temp in these cases. Signed-off-by: Peter Maydell --- target-arm/translate.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index e79ea03..527e260 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3810,7 +3810,6 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) rn = (insn >> 16) & 0xf; rm = insn & 0xf; load = (insn & (1 << 21)) != 0; - addr = tcg_temp_new_i32(); if ((insn & (1 << 23)) == 0) { /* Load store all elements. */ op = (insn >> 8) & 0xf; @@ -3822,6 +3821,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) spacing = neon_ls_element_type[op].spacing; if (size == 3 && (interleave | spacing) != 1) return 1; + addr = tcg_temp_new_i32(); load_reg_var(s, addr, rn); stride = (1 << size) * interleave; for (reg = 0; reg < nregs; reg++) { @@ -3907,6 +3907,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) } rd += spacing; } + tcg_temp_free_i32(addr); stride = nregs * 8; } else { size = (insn >> 10) & 3; @@ -3932,6 +3933,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) if (nregs == 3 && a == 1) { return 1; } + addr = tcg_temp_new_i32(); load_reg_var(s, addr, rn); if (nregs == 1) { /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */ @@ -3955,6 +3957,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) rd += stride; } } + tcg_temp_free_i32(addr); stride = (1 << size) * nregs; } else { /* Single element. */ @@ -3976,6 +3979,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) abort(); } nregs = ((insn >> 8) & 3) + 1; + addr = tcg_temp_new_i32(); load_reg_var(s, addr, rn); for (reg = 0; reg < nregs; reg++) { if (load) { @@ -4017,10 +4021,10 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) rd += stride; tcg_gen_addi_i32(addr, addr, 1 << size); } + tcg_temp_free_i32(addr); stride = nregs * (1 << size); } } - tcg_temp_free_i32(addr); if (rm != 15) { TCGv base;