From patchwork Mon Feb 21 11:05:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 83824 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 80786B6EEA for ; Mon, 21 Feb 2011 22:13:05 +1100 (EST) Received: from localhost ([127.0.0.1]:39660 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PrThN-0002CE-LZ for incoming@patchwork.ozlabs.org; Mon, 21 Feb 2011 06:13:01 -0500 Received: from [140.186.70.92] (port=36977 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PrTa3-0004ad-9I for qemu-devel@nongnu.org; Mon, 21 Feb 2011 06:05:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PrTa1-0004qC-3e for qemu-devel@nongnu.org; Mon, 21 Feb 2011 06:05:26 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:46016) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PrTa0-0004pt-Mh for qemu-devel@nongnu.org; Mon, 21 Feb 2011 06:05:25 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1PrTZy-0004Kn-61; Mon, 21 Feb 2011 11:05:22 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 21 Feb 2011 11:05:22 +0000 Message-Id: <1298286322-16634-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1298286322-16634-1-git-send-email-peter.maydell@linaro.org> References: <1298286322-16634-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: patches@linaro.org Subject: [Qemu-devel] [PATCH v3 2/2] target-arm: Fix shift by immediate and narrow where src, dest overlap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org For Neon shifts by immediate and narrow, correctly handle the case where the source registers and the destination registers overlap (the second pass should use the original register contents, not the results of the first pass). This includes a refactoring to pull the size check outside the loop rather than inside, since there is now very little common code between the size == 3 and size != 3 case. Signed-off-by: Peter Maydell --- target-arm/translate.c | 84 +++++++++++++++++++++++++----------------------- 1 files changed, 44 insertions(+), 40 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index fa20e84..dbd958b 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4804,64 +4804,68 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) shift = shift - (1 << (size + 3)); size++; - switch (size) { - case 1: - imm = (uint16_t)shift; - imm |= imm << 16; - tmp2 = tcg_const_i32(imm); - TCGV_UNUSED_I64(tmp64); - break; - case 2: - imm = (uint32_t)shift; - tmp2 = tcg_const_i32(imm); - TCGV_UNUSED_I64(tmp64); - break; - case 3: + if (size == 3) { tmp64 = tcg_const_i64(shift); - TCGV_UNUSED(tmp2); - break; - default: - abort(); - } - - for (pass = 0; pass < 2; pass++) { - if (size == 3) { - neon_load_reg64(cpu_V0, rm + pass); + neon_load_reg64(cpu_V0, rm); + neon_load_reg64(cpu_V1, rm + 1); + for (pass = 0; pass < 2; pass++) { + TCGv_i64 in; + if (pass == 0) { + in = cpu_V0; + } else { + in = cpu_V1; + } if (q) { if (input_unsigned) { - gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, - tmp64); + gen_helper_neon_rshl_u64(cpu_V0, in, tmp64); } else { - gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, - tmp64); + gen_helper_neon_rshl_s64(cpu_V0, in, tmp64); } } else { if (input_unsigned) { - gen_helper_neon_shl_u64(cpu_V0, cpu_V0, - tmp64); + gen_helper_neon_shl_u64(cpu_V0, in, tmp64); } else { - gen_helper_neon_shl_s64(cpu_V0, cpu_V0, - tmp64); + gen_helper_neon_shl_s64(cpu_V0, in, tmp64); } } + tmp = new_tmp(); + gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0); + neon_store_reg(rd, pass, tmp); + } /* for pass */ + tcg_temp_free_i64(tmp64); + } else { + if (size == 1) { + imm = (uint16_t)shift; + imm |= imm << 16; } else { - tmp = neon_load_reg(rm + pass, 0); + /* size == 2 */ + imm = (uint32_t)shift; + } + tmp2 = tcg_const_i32(imm); + tmp4 = neon_load_reg(rm + 1, 0); + tmp5 = neon_load_reg(rm + 1, 1); + for (pass = 0; pass < 2; pass++) { + if (pass == 0) { + tmp = neon_load_reg(rm, 0); + } else { + tmp = tmp4; + } gen_neon_shift_narrow(size, tmp, tmp2, q, input_unsigned); - tmp3 = neon_load_reg(rm + pass, 1); + if (pass == 0) { + tmp3 = neon_load_reg(rm, 1); + } else { + tmp3 = tmp5; + } gen_neon_shift_narrow(size, tmp3, tmp2, q, input_unsigned); tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3); dead_tmp(tmp); dead_tmp(tmp3); - } - tmp = new_tmp(); - gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0); - neon_store_reg(rd, pass, tmp); - } /* for pass */ - if (size == 3) { - tcg_temp_free_i64(tmp64); - } else { + tmp = new_tmp(); + gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0); + neon_store_reg(rd, pass, tmp); + } /* for pass */ tcg_temp_free_i32(tmp2); } } else if (op == 10) {