From patchwork Wed Feb 9 16:27:27 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 82502 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A2D3DB70EA for ; Thu, 10 Feb 2011 03:52:32 +1100 (EST) Received: from localhost ([127.0.0.1]:54868 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PnDHJ-0004XN-7u for incoming@patchwork.ozlabs.org; Wed, 09 Feb 2011 11:52:29 -0500 Received: from [140.186.70.92] (port=57433 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PnD6A-0000YP-29 for qemu-devel@nongnu.org; Wed, 09 Feb 2011 11:40:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PnD68-0008PV-VD for qemu-devel@nongnu.org; Wed, 09 Feb 2011 11:40:57 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:52218) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PnD68-0008Oa-Hn for qemu-devel@nongnu.org; Wed, 09 Feb 2011 11:40:56 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PnCt8-0001Vg-H2; Wed, 09 Feb 2011 16:27:30 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Wed, 9 Feb 2011 16:27:27 +0000 Message-Id: <1297268850-5777-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1297268850-5777-1-git-send-email-peter.maydell@linaro.org> References: <1297268850-5777-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Christophe Lyon , patches@linaro.org Subject: [Qemu-devel] [PATCH v2 3/6] softfloat: Fix single-to-half precision float conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fix various bugs in the single-to-half-precision conversion code: * input NaNs not correctly converted in IEEE mode (fixed by defining and using a commonNaNToFloat16()) * wrong values returned when converting NaN/Inf into non-IEEE half precision value * wrong values returned for conversion of values which are on the boundary between denormal and zero for the half precision format * zeroes not correctly identified * excessively large results in non-IEEE mode should generate InvalidOp, not Overflow Signed-off-by: Peter Maydell --- fpu/softfloat-specialize.h | 20 ++++++++++++++++++++ fpu/softfloat.c | 30 ++++++++++++++++++------------ 2 files changed, 38 insertions(+), 12 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 2f65b9d..4907484 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -116,6 +116,26 @@ float16 float16_maybe_silence_nan(float16 a) } /*---------------------------------------------------------------------------- +| Returns the result of converting the canonical NaN `a' to the half- +| precision floating-point format. +*----------------------------------------------------------------------------*/ + +static float16 commonNaNToFloat16(commonNaNT a STATUS_PARAM) +{ + uint16_t mantissa = a.high>>54; + + if (STATUS(default_nan_mode)) { + return float16_default_nan; + } + + if (mantissa) { + return ((((uint16_t) a.sign) << 15) | (0x1F << 10) | mantissa); + } else { + return float16_default_nan; + } +} + +/*---------------------------------------------------------------------------- | The pattern for a default generated single-precision NaN. *----------------------------------------------------------------------------*/ #if defined(TARGET_SPARC) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index c3058f4..4d51428 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2767,25 +2767,31 @@ float16 float32_to_float16(float32 a, flag ieee STATUS_PARAM) aExp = extractFloat32Exp( a ); aSign = extractFloat32Sign( a ); if ( aExp == 0xFF ) { - if (aSig) { - /* Make sure correct exceptions are raised. */ - float32ToCommonNaN(a STATUS_VAR); - aSig |= 0x00400000; + if ( aSig ) { + /* Input is a NaN */ + bits16 r = commonNaNToFloat16( float32ToCommonNaN( a STATUS_VAR ) STATUS_VAR ); + if (!ieee) { + return packFloat16(aSign, 0, 0); + } + return r; } - return packFloat16(aSign, 0x1f, aSig >> 13); + /* Infinity */ + if (!ieee) { + float_raise(float_flag_invalid STATUS_VAR); + return packFloat16(aSign, 0x1f, 0x3ff); + } + return packFloat16(aSign, 0x1f, 0); } - if (aExp == 0 && aSign == 0) { + if (aExp == 0 && aSig == 0) { return packFloat16(aSign, 0, 0); } /* Decimal point between bits 22 and 23. */ aSig |= 0x00800000; aExp -= 0x7f; if (aExp < -14) { - mask = 0x007fffff; - if (aExp < -24) { - aExp = -25; - } else { - mask >>= 24 + aExp; + mask = 0x00ffffff; + if (aExp >= -24) { + mask >>= 25 + aExp; } } else { mask = 0x00001fff; @@ -2827,7 +2833,7 @@ float16 float32_to_float16(float32 a, flag ieee STATUS_PARAM) } } else { if (aExp > 16) { - float_raise( float_flag_overflow | float_flag_inexact STATUS_VAR); + float_raise(float_flag_invalid | float_flag_inexact STATUS_VAR); return packFloat16(aSign, 0x1f, 0x3ff); } }