From patchwork Thu Jan 27 07:32:10 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 80606 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2FAD3B711E for ; Thu, 27 Jan 2011 18:37:24 +1100 (EST) Received: from localhost ([127.0.0.1]:38772 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PiMPw-00005p-NK for incoming@patchwork.ozlabs.org; Thu, 27 Jan 2011 02:37:21 -0500 Received: from [140.186.70.92] (port=41191 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PiML0-0007PC-Ef for qemu-devel@nongnu.org; Thu, 27 Jan 2011 02:32:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PiMKy-0002Er-UH for qemu-devel@nongnu.org; Thu, 27 Jan 2011 02:32:14 -0500 Received: from hall.aurel32.net ([88.191.126.93]:52669) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PiMKy-0002Dz-Pa for qemu-devel@nongnu.org; Thu, 27 Jan 2011 02:32:12 -0500 Received: from [2001:470:d4ed:0:5e26:aff:fe2b:6f5b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1PiMKw-00032w-Fh; Thu, 27 Jan 2011 08:32:10 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.72) (envelope-from ) id 1PiMKx-00031D-P6; Thu, 27 Jan 2011 08:32:11 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Thu, 27 Jan 2011 08:32:10 +0100 Message-Id: <1296113530-11573-1-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.2.3 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Blue Swirl , Aurelien Jarno Subject: [Qemu-devel] [PATCH] escc: fix interrupt flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Recent PowerPC kernel end up in kernel panic during boot in -nographic mode. In this mode the second serial port is used as the udbg console, and thus a few characters are sent on this port. This activates the tx interrupt flag, and later choke the Linux kernel, as it was not expecting such a flag to be set. The problem here comes from the fact that contrary to most devices the interrupt flags are only set if the interrupt is enabled. Quoting the datasheet: "If the corresponding IE bit is not set, the IP for that source of interrupt will never be set." This patch fixes that by enabling the interrupt flag only when the corresponding interrupt is enabled. Cc: Blue Swirl Signed-off-by: Aurelien Jarno Acked-by: Blue Swirl --- hw/escc.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/escc.c b/hw/escc.c index ba60636..f6fd919 100644 --- a/hw/escc.c +++ b/hw/escc.c @@ -369,14 +369,18 @@ static inline void set_txint(ChannelState *s) if (!s->rxint_under_svc) { s->txint_under_svc = 1; if (s->chn == chn_a) { - s->rregs[R_INTR] |= INTR_TXINTA; + if (s->wregs[W_INTR] & INTR_TXINT) { + s->rregs[R_INTR] |= INTR_TXINTA; + } if (s->wregs[W_MINTR] & MINTR_STATUSHI) s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA; else s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA; } else { s->rregs[R_IVEC] = IVEC_TXINTB; - s->otherchn->rregs[R_INTR] |= INTR_TXINTB; + if (s->wregs[W_INTR] & INTR_TXINT) { + s->otherchn->rregs[R_INTR] |= INTR_TXINTB; + } } escc_update_irq(s); }