@@ -443,12 +443,27 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
+ int privmode;
*pc = env->regs[15];
*cs_base = 0;
+ /* flags word usage:
+ * [0] thumbstate
+ * [3..1] vec_len
+ * [5..4] vec_stride
+ * [6] privileged (ie not user) mode
+ * [7] VFP enable bit
+ * [15..8] condexec bits
+ */
*flags = env->thumb | (env->vfp.vec_len << 1)
| (env->vfp.vec_stride << 4) | (env->condexec_bits << 8);
- if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
+ } else {
+ privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
+ }
+ if (privmode) {
*flags |= (1 << 6);
+ }
if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
*flags |= (1 << 7);
}
M profile ARM cores don't have a CPSR mode field. Set the bit in the TB flags that indicates non-user mode correctly for these cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/cpu.h | 17 ++++++++++++++++- 1 files changed, 16 insertions(+), 1 deletions(-)