From patchwork Wed Dec 29 21:27:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 76948 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 03E45B6F1E for ; Thu, 30 Dec 2010 08:29:19 +1100 (EST) Received: from localhost ([127.0.0.1]:50718 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PY3a8-0000ZZ-9b for incoming@patchwork.ozlabs.org; Wed, 29 Dec 2010 16:29:16 -0500 Received: from [140.186.70.92] (port=34904 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PY3YO-0008QK-HP for qemu-devel@nongnu.org; Wed, 29 Dec 2010 16:27:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PY3YN-0006Ks-Bm for qemu-devel@nongnu.org; Wed, 29 Dec 2010 16:27:28 -0500 Received: from hall.aurel32.net ([88.191.126.93]:60173) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PY3YN-0006Km-2u for qemu-devel@nongnu.org; Wed, 29 Dec 2010 16:27:27 -0500 Received: from farad.aurel32.net ([82.232.2.251] helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1PY3YM-0007Cg-Hr; Wed, 29 Dec 2010 22:27:26 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.72) (envelope-from ) id 1PY3YL-0002fm-LX; Wed, 29 Dec 2010 22:27:25 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 29 Dec 2010 22:27:24 +0100 Message-Id: <1293658044-10244-1-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.2.3 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH] TCG: Improve tb_phys_hash_func() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Most of emulated CPU have instructions aligned on 16 or 32 bits, while on others GCC tries to align the target jump location. This means that 1/2 or 3/4 of tb_phys_hash entries are never used. Update the hash function tb_phys_hash_func() to ignore the two lowest bits of the address. This brings a 6% speed-up when booting a MIPS image. Signed-off-by: Aurelien Jarno --- exec-all.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/exec-all.h b/exec-all.h index 6821b17..a4b75bd 100644 --- a/exec-all.h +++ b/exec-all.h @@ -177,7 +177,7 @@ static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) { - return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); + return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1); } TranslationBlock *tb_alloc(target_ulong pc);