From patchwork Sun Oct 17 09:45:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gleb Natapov X-Patchwork-Id: 68071 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 12346B70EF for ; Sun, 17 Oct 2010 20:47:23 +1100 (EST) Received: from localhost ([127.0.0.1]:54725 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P7Ppo-0003SH-6D for incoming@patchwork.ozlabs.org; Sun, 17 Oct 2010 05:47:20 -0400 Received: from [140.186.70.92] (port=59203 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P7Po2-0003S5-Tw for qemu-devel@nongnu.org; Sun, 17 Oct 2010 05:45:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P7Po1-0007xI-RT for qemu-devel@nongnu.org; Sun, 17 Oct 2010 05:45:30 -0400 Received: from mx1.redhat.com ([209.132.183.28]:27876) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P7Po1-0007wf-L2 for qemu-devel@nongnu.org; Sun, 17 Oct 2010 05:45:29 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id o9H9jR9U011885 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Sun, 17 Oct 2010 05:45:27 -0400 Received: from dhcp-1-237.tlv.redhat.com (dhcp-1-237.tlv.redhat.com [10.35.1.237]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id o9H9jQ1c004593 for ; Sun, 17 Oct 2010 05:45:27 -0400 Received: by dhcp-1-237.tlv.redhat.com (Postfix, from userid 13519) id 0347718D46E; Sun, 17 Oct 2010 11:45:25 +0200 (IST) From: Gleb Natapov To: qemu-devel@nongnu.org Date: Sun, 17 Oct 2010 11:45:25 +0200 Message-Id: <1287308725-30811-2-git-send-email-gleb@redhat.com> In-Reply-To: <1287308725-30811-1-git-send-email-gleb@redhat.com> References: <1287308725-30811-1-git-send-email-gleb@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. Subject: [Qemu-devel] [PATCH 2/2] Fix pci hotplug to generate level triggered interrupt. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org SCI is level triggered. pci hotplug should behave appropriately. Signed-off-by: Gleb Natapov --- hw/acpi_piix4.c | 28 +++++++++++++++++----------- 1 files changed, 17 insertions(+), 11 deletions(-) diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c index bec42b4..f74f34c 100644 --- a/hw/acpi_piix4.c +++ b/hw/acpi_piix4.c @@ -107,7 +107,9 @@ static void pm_update_sci(PIIX4PMState *s) (ACPI_BITMASK_RT_CLOCK_ENABLE | ACPI_BITMASK_POWER_BUTTON_ENABLE | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | - ACPI_BITMASK_TIMER_ENABLE)) != 0); + ACPI_BITMASK_TIMER_ENABLE)) != 0) || + (((s->gpe.sts & s->gpe.en) & PIIX4_PCI_HOTPLUG_STATUS) != 0); + qemu_set_irq(s->irq, sci_level); /* schedule a timer interruption if needed */ if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) && @@ -462,7 +464,9 @@ static uint32_t gpe_read_val(uint16_t val, uint32_t addr) static uint32_t gpe_readb(void *opaque, uint32_t addr) { uint32_t val = 0; - struct gpe_regs *g = opaque; + PIIX4PMState *s = opaque; + struct gpe_regs *g = &s->gpe; + switch (addr) { case GPE_BASE: case GPE_BASE + 1: @@ -502,7 +506,9 @@ static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val) static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) { - struct gpe_regs *g = opaque; + PIIX4PMState *s = opaque; + struct gpe_regs *g = &s->gpe; + switch (addr) { case GPE_BASE: case GPE_BASE + 1: @@ -514,7 +520,9 @@ static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) break; default: break; - } + } + + pm_update_sci(s); PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); } @@ -581,11 +589,10 @@ static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state); static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) { - struct gpe_regs *gpe = &s->gpe; struct pci_status *pci0_status = &s->pci0_status; - register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, gpe); - register_ioport_read(GPE_BASE, 4, 1, gpe_readb, gpe); + register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s); + register_ioport_read(GPE_BASE, 4, 1, gpe_readb, s); register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status); register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status); @@ -621,9 +628,8 @@ static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state) } else { disable_device(s, slot); } - if (s->gpe.en & 2) { - qemu_set_irq(s->irq, 1); - qemu_set_irq(s->irq, 0); - } + + pm_update_sci(s); + return 0; }