From patchwork Fri Jun 4 19:14:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 54694 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4E189B7D1C for ; Sat, 5 Jun 2010 06:00:05 +1000 (EST) Received: from localhost ([127.0.0.1]:38118 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcrG-0004NY-Oc for incoming@patchwork.ozlabs.org; Fri, 04 Jun 2010 15:47:10 -0400 Received: from [140.186.70.92] (port=59207 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcOS-0006DU-1g for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:17:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OKcOQ-0002en-Nl for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:17:23 -0400 Received: from are.twiddle.net ([75.149.56.221]:54824) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OKcOQ-0002eb-G3 for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:17:22 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id E8EB6F7B; Fri, 4 Jun 2010 12:17:21 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o54JHLhL007322; Fri, 4 Jun 2010 12:17:21 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o54JHKMg007321; Fri, 4 Jun 2010 12:17:20 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 4 Jun 2010 12:14:41 -0700 Message-Id: <1275678883-7082-34-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1275678883-7082-1-git-send-email-rth@twiddle.net> References: <1275678883-7082-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 33/35] tcg-s390: Use the COMPARE IMMEDIATE instrucions for compares. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org These instructions are available with extended-immediate facility. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 44 ++++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 42 insertions(+), 2 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index 8bc82b4..691a3f5 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -75,6 +75,10 @@ typedef enum S390Opcode { RIL_ALGFI = 0xc20a, RIL_BRASL = 0xc005, RIL_BRCL = 0xc004, + RIL_CFI = 0xc20d, + RIL_CGFI = 0xc20c, + RIL_CLFI = 0xc20f, + RIL_CLGFI = 0xc20e, RIL_IIHF = 0xc008, RIL_IILF = 0xc009, RIL_LARL = 0xc000, @@ -533,7 +537,29 @@ static int tcg_match_xori(int ct, tcg_target_long val) static int tcg_match_cmpi(int ct, tcg_target_long val) { - return (val == 0); + if (facilities & FACILITY_EXT_IMM) { + /* The COMPARE IMMEDIATE instruction is available. */ + if (ct & TCG_CT_CONST_32) { + /* We have a 32-bit immediate and can compare against anything. */ + return 1; + } else { + /* ??? We have no insight here into whether the comparison is + signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit + signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses + a 32-bit unsigned immediate. If we were to use the (semi) + obvious "val == (int32_t)val" we would be enabling unsigned + comparisons vs very large numbers. The only solution is to + take the intersection of the ranges. */ + /* ??? Another possible solution is to simply lie and allow all + constants here and force the out-of-range values into a temp + register in tgen_cmp when we have knowledge of the actual + comparison code in use. */ + return val >= 0 && val <= 0x7fffffff; + } + } else { + /* Only the LOAD AND TEST instruction is available. */ + return val == 0; + } } /* Test if a constant matches the constraint. */ @@ -1093,7 +1119,21 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, } return tcg_cond_to_ltr_cond[c]; } else { - tcg_abort(); + if (c > TCG_COND_GT) { + /* unsigned */ + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RIL, CLFI, r1, c2); + } else { + tcg_out_insn(s, RIL, CLGFI, r1, c2); + } + } else { + /* signed */ + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RIL, CFI, r1, c2); + } else { + tcg_out_insn(s, RIL, CGFI, r1, c2); + } + } } } else { if (c > TCG_COND_GT) {