From patchwork Fri Jun 4 19:14:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 54683 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CE12CB7D1C for ; Sat, 5 Jun 2010 05:42:20 +1000 (EST) Received: from localhost ([127.0.0.1]:40618 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcjS-0001DD-8y for incoming@patchwork.ozlabs.org; Fri, 04 Jun 2010 15:39:06 -0400 Received: from [140.186.70.92] (port=37730 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcNR-0005OI-KC for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:16:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OKcNQ-0002NN-5U for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:16:21 -0400 Received: from are.twiddle.net ([75.149.56.221]:54782) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OKcNP-0002Mv-54 for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:16:20 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id B61F4F7B; Fri, 4 Jun 2010 12:16:16 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o54JGEtH007241; Fri, 4 Jun 2010 12:16:14 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o54JGBMQ007240; Fri, 4 Jun 2010 12:16:11 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 4 Jun 2010 12:14:24 -0700 Message-Id: <1275678883-7082-17-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1275678883-7082-1-git-send-email-rth@twiddle.net> References: <1275678883-7082-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 16/35] tcg-s390: Re-implement tcg_out_movi. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Make better use of the LOAD HALFWORD IMMEDIATE, LOAD IMMEDIATE, and INSERT IMMEDIATE instruction groups. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 129 +++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 113 insertions(+), 16 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index d99bb5c..71e017a 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -52,12 +52,23 @@ typedef enum S390Opcode { RIL_BRASL = 0xc005, RIL_BRCL = 0xc004, RIL_LARL = 0xc000, + RIL_IIHF = 0xc008, + RIL_IILF = 0xc009, + RIL_LGFI = 0xc001, + RIL_LLIHF = 0xc00e, + RIL_LLILF = 0xc00f, RI_AGHI = 0xa70b, RI_AHI = 0xa70a, RI_BRC = 0xa704, + RI_IIHH = 0xa500, + RI_IIHL = 0xa501, RI_IILH = 0xa502, + RI_IILL = 0xa503, RI_LGHI = 0xa709, + RI_LLIHH = 0xa50c, + RI_LLIHL = 0xa50d, + RI_LLILH = 0xa50e, RI_LLILL = 0xa50f, RRE_AGR = 0xb908, @@ -382,24 +393,110 @@ static inline void tcg_out_mov(TCGContext *s, int ret, int arg) } /* load a register with an immediate value */ -static inline void tcg_out_movi(TCGContext *s, TCGType type, - int ret, tcg_target_long arg) +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long sval) { - if (arg >= -0x8000 && arg < 0x8000) { /* signed immediate load */ - tcg_out_insn(s, RI, LGHI, ret, arg); - } else if (!(arg & 0xffffffffffff0000UL)) { - tcg_out_insn(s, RI, LLILL, ret, arg); - } else if (!(arg & 0xffffffff00000000UL) || type == TCG_TYPE_I32) { - tcg_out_insn(s, RI, LLILL, ret, arg); - tcg_out_insn(s, RI, IILH, ret, arg >> 16); + static const S390Opcode lli_insns[4] = { + RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH + }; + + tcg_target_ulong uval = sval; + int i; + + if (type == TCG_TYPE_I32) { + uval = (uint32_t)sval; + sval = (int32_t)sval; + } + + /* Try all 32-bit insns that can load it in one go. */ + if (sval >= -0x8000 && sval < 0x8000) { + tcg_out_insn(s, RI, LGHI, ret, sval); + return; + } + + for (i = 0; i < 4; i++) { + tcg_target_long mask = 0xffffull << i*16; + if ((uval & mask) != 0 && (uval & ~mask) == 0) { + tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16); + return; + } + } + + /* Try all 48-bit insns that can load it in one go. */ + if (facilities & FACILITY_EXT_IMM) { + if (sval == (int32_t)sval) { + tcg_out_insn(s, RIL, LGFI, ret, sval); + return; + } + if (uval <= 0xffffffff) { + tcg_out_insn(s, RIL, LLILF, ret, uval); + return; + } + if ((uval & 0xffffffff) == 0) { + tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32); + return; + } + } + + /* Try for PC-relative address load. */ + if ((sval & 1) == 0) { + intptr_t off = (sval - (intptr_t)s->code_ptr) >> 1; + if (off == (int32_t)off) { + tcg_out_insn(s, RIL, LARL, ret, off); + return; + } + } + + /* If extended immediates are not present, then we may have to issue + several instructions to load the low 32 bits. */ + if (!(facilities & FACILITY_EXT_IMM)) { + /* A 32-bit unsigned value can be loaded in 2 insns. And given + that the lli_insns loop above did not succeed, we know that + both insns are required. */ + if (uval <= 0xffffffff) { + tcg_out_insn(s, RI, LLILL, ret, uval); + tcg_out_insn(s, RI, IILH, ret, uval >> 16); + return; + } + + /* If all high bits are set, the value can be loaded in 2 or 3 insns. + We first want to make sure that all the high bits get set. With + luck the low 16-bits can be considered negative to perform that for + free, otherwise we load an explicit -1. */ + if (sval >> 32 == -1) { + if (uval & 0x8000) { + tcg_out_insn(s, RI, LGHI, ret, uval); + } else { + tcg_out_insn(s, RI, LGHI, ret, -1); + tcg_out_insn(s, RI, IILL, ret, uval); + } + tcg_out_insn(s, RI, IILH, ret, uval >> 16); + return; + } + } + + /* If we get here, both the high and low parts have non-zero bits. */ + + /* Recurse to load the lower 32-bits. */ + tcg_out_movi(s, TCG_TYPE_I32, ret, sval); + + /* Insert data into the high 32-bits. */ + uval >>= 32; + if (facilities & FACILITY_EXT_IMM) { + if (uval < 0x10000) { + tcg_out_insn(s, RI, IIHL, ret, uval); + } else if ((uval & 0xffff) == 0) { + tcg_out_insn(s, RI, IIHH, ret, uval >> 16); + } else { + tcg_out_insn(s, RIL, IIHF, ret, uval); + } } else { - /* branch over constant and store its address in R13 */ - tcg_out_insn(s, RIL, BRASL, TCG_TMP0, (6 + 8) >> 1); - /* 64-bit constant */ - tcg_out32(s, arg >> 32); - tcg_out32(s, arg); - /* load constant to ret */ - tcg_out_insn(s, RXY, LG, ret, TCG_TMP0, 0, 0); + if (uval & 0xffff) { + tcg_out_insn(s, RI, IIHL, ret, uval); + } + if (uval & 0xffff0000) { + tcg_out_insn(s, RI, IIHH, ret, uval >> 16); + } } }