From patchwork Thu May 27 20:46:16 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 53820 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6D20AB7D20 for ; Fri, 28 May 2010 07:46:00 +1000 (EST) Received: from localhost ([127.0.0.1]:58883 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHksD-0001Hr-Rq for incoming@patchwork.ozlabs.org; Thu, 27 May 2010 17:44:17 -0400 Received: from [140.186.70.92] (port=56170 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHjzL-0002AQ-2b for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OHjzJ-0005OU-ST for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:34 -0400 Received: from are.twiddle.net ([75.149.56.221]:51236) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OHjzJ-0005OI-NJ for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:33 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id 2A8E447E; Thu, 27 May 2010 13:47:33 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o4RKlWH6030973; Thu, 27 May 2010 13:47:32 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o4RKlVmQ030972; Thu, 27 May 2010 13:47:31 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 May 2010 13:46:16 -0700 Message-Id: <1274993204-30766-35-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1274993204-30766-1-git-send-email-rth@twiddle.net> References: <1274993204-30766-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 34/62] tcg-s390: Implement immediate MULs. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 28 ++++++++++++++++++++++++---- 1 files changed, 24 insertions(+), 4 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index 2a9d64d..1bc9b4c 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -51,6 +51,8 @@ typedef enum S390Opcode { RIL_LGFI = 0xc001, RIL_LLIHF = 0xc00e, RIL_LLILF = 0xc00f, + RIL_MSFI = 0xc201, + RIL_MSGFI = 0xc200, RIL_NIHF = 0xc00a, RIL_NILF = 0xc00b, RIL_OIHF = 0xc00c, @@ -68,6 +70,8 @@ typedef enum S390Opcode { RI_LLIHL = 0xa50d, RI_LLILH = 0xa50e, RI_LLILL = 0xa50f, + RI_MGHI = 0xa70d, + RI_MHI = 0xa70c, RI_NIHH = 0xa504, RI_NIHL = 0xa505, RI_NILH = 0xa506, @@ -1227,10 +1231,26 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mul_i32: - tcg_out_insn(s, RRE, MSR, args[0], args[2]); + if (const_args[2]) { + if (args[2] == (int16_t)args[2]) { + tcg_out_insn(s, RI, MHI, args[0], args[2]); + } else { + tcg_out_insn(s, RIL, MSFI, args[0], args[2]); + } + } else { + tcg_out_insn(s, RRE, MSR, args[0], args[2]); + } break; case INDEX_op_mul_i64: - tcg_out_insn(s, RRE, MSGR, args[0], args[2]); + if (const_args[2]) { + if (args[2] == (int16_t)args[2]) { + tcg_out_insn(s, RI, MGHI, args[0], args[2]); + } else { + tcg_out_insn(s, RIL, MSGFI, args[0], args[2]); + } + } else { + tcg_out_insn(s, RRE, MSGR, args[0], args[2]); + } break; case INDEX_op_div2_i32: @@ -1463,7 +1483,7 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_add_i32, { "r", "0", "ri" } }, { INDEX_op_sub_i32, { "r", "0", "ri" } }, - { INDEX_op_mul_i32, { "r", "0", "r" } }, + { INDEX_op_mul_i32, { "r", "0", "ri" } }, { INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } }, { INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } }, @@ -1524,7 +1544,7 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_add_i64, { "r", "0", "rI" } }, { INDEX_op_sub_i64, { "r", "0", "rJ" } }, - { INDEX_op_mul_i64, { "r", "0", "r" } }, + { INDEX_op_mul_i64, { "r", "0", "rI" } }, { INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } }, { INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } },