From patchwork Sat May 22 08:38:56 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artyom Tarasenko X-Patchwork-Id: 53261 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4D7A3B7D24 for ; Sat, 22 May 2010 19:01:04 +1000 (EST) Received: from localhost ([127.0.0.1]:58944 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OFkZp-0007xF-Do for incoming@patchwork.ozlabs.org; Sat, 22 May 2010 05:01:01 -0400 Received: from [140.186.70.92] (port=48925 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OFkEY-0006Da-4Q for qemu-devel@nongnu.org; Sat, 22 May 2010 04:39:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OFkEW-0002zl-8p for qemu-devel@nongnu.org; Sat, 22 May 2010 04:39:01 -0400 Received: from fg-out-1718.google.com ([72.14.220.158]:46733) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OFkEV-0002zb-Ns for qemu-devel@nongnu.org; Sat, 22 May 2010 04:39:00 -0400 Received: by fg-out-1718.google.com with SMTP id 16so1086945fgg.10 for ; Sat, 22 May 2010 01:38:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=aQCkEIU8IwKl5Velzr0V4c6FCQIrcnBTrxaYa4cN97w=; b=xLciv2BtZzu+EhR61DUtHqmoz/dAcAzfzW42930PbUNiLG2cnd8N5BguzCHaptU0Nk LdkZ+KhEavYjBWzySl5DKGs7N9EzEubGJSdTC7zLmPvsapsxIu64sh8aAKOwOieya2XU 3arl7fa3Gp6UwK1x1Wu9PU5CL1pDjOZUvoPEc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=E40f+EcTevnXI9RjgE0R0v7Bgx5jYWmEnR5v+Fu63Y5tXB3fEBjh4fUb78ZKXX5fR1 hbgbhCrY5cG6jcY2rvdzNXYuxMO2kONgMJECQoNck2YrFSpaWSg4n6lNU0nR31jjo413 YdiUvmGEdTC2W9CypZYspZdVRAuNoiVipFKhU= Received: by 10.86.22.31 with SMTP id 31mr5060343fgv.24.1274517538827; Sat, 22 May 2010 01:38:58 -0700 (PDT) Received: from localhost (e180188134.adsl.alicedsl.de [85.180.188.134]) by mx.google.com with ESMTPS id 1sm2683183fkt.11.2010.05.22.01.38.57 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 22 May 2010 01:38:58 -0700 (PDT) From: Artyom Tarasenko To: qemu-devel@nongnu.org Date: Sat, 22 May 2010 10:38:56 +0200 Message-Id: <1274517536-20889-1-git-send-email-atar4qemu@gmail.com> X-Mailer: git-send-email 1.6.2.5 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: blauwirbel@gmail.com, Artyom Tarasenko Subject: [Qemu-devel] [PATCH] sparc32 protect read-only bits in DMA CSR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On a real hardware changing read-only bits has no effect Use a mask common for SCSI and Ethernet registers. The crucial bit is DMA_INTR, because setting or clearing it may produce spurious interrupts. This patch allows booting Solaris 2.3 --- hw/sparc32_dma.c | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c index 3ceb851..b521707 100644 --- a/hw/sparc32_dma.c +++ b/hw/sparc32_dma.c @@ -62,6 +62,9 @@ #define DMA_DRAIN_FIFO 0x40 #define DMA_RESET 0x80 +/* XXX SCSI and ethernet should have different read-only bit masks */ +#define DMA_CSR_RO_MASK 0xfe000007 + typedef struct DMAState DMAState; struct DMAState { @@ -187,7 +190,7 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) switch (saddr) { case 0: if (val & DMA_INTREN) { - if (val & DMA_INTR) { + if (s->dmaregs[0] & DMA_INTR) { DPRINTF("Raise IRQ\n"); qemu_irq_raise(s->irq); } @@ -204,16 +207,17 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) val &= ~DMA_DRAIN_FIFO; } else if (val == 0) val = DMA_DRAIN_FIFO; - val &= 0x0fffffff; + val &= ~DMA_CSR_RO_MASK; val |= DMA_VER; + s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val; break; case 1: s->dmaregs[0] |= DMA_LOADED; - break; + /* fall through */ default: + s->dmaregs[saddr] = val; break; } - s->dmaregs[saddr] = val; } static CPUReadMemoryFunc * const dma_mem_read[3] = {