From patchwork Mon May 10 23:19:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: QiaoChong X-Patchwork-Id: 52248 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 96D55B7D73 for ; Tue, 11 May 2010 09:21:52 +1000 (EST) Received: from localhost ([127.0.0.1]:49635 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OBcIH-0003L6-Ge for incoming@patchwork.ozlabs.org; Mon, 10 May 2010 19:21:49 -0400 Received: from [140.186.70.92] (port=42293 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OBcGE-00030I-OK for qemu-devel@nongnu.org; Mon, 10 May 2010 19:19:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OBcGC-0007Zi-Ff for qemu-devel@nongnu.org; Mon, 10 May 2010 19:19:42 -0400 Received: from [159.226.40.154] (port=42992 helo=mail.loongson.cn) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OBcGB-0007XQ-Nv for qemu-devel@nongnu.org; Mon, 10 May 2010 19:19:40 -0400 Received: from localhost.localdomain (unknown [10.2.1.99]) by mail.loongson.cn (Postfix) with ESMTPA id 9C9E3C6233; Tue, 11 May 2010 07:19:23 +0800 (CST) From: QiaoChong To: qemu-devel@nongnu.org Date: Tue, 11 May 2010 07:19:04 +0800 Message-Id: <1273533547-21789-4-git-send-email-qiaochong@loongson.cn> X-Mailer: git-send-email 1.7.0.3.254.g4503b.dirty In-Reply-To: <1273533547-21789-1-git-send-email-qiaochong@loongson.cn> References: <1273533547-21789-1-git-send-email-qiaochong@loongson.cn> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 1) Cc: QiaoChong , joro@8bytes.org, herbszt@gmx.de, agraf@suse.de, elek.roland@gmail.com Subject: [Qemu-devel] [PATCH 3/6] fix port count, cap and version etc to ahci. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Sebastian Herbszt - debug output with DEBUG_AHCI - set port count to 4 - change return value of PxSSTS to include SPD and IPM - change cap and version default values according to Intel #301473-002 Signed-off-by: QiaoChong --- hw/ahci.c | 68 ++++++++++++++++++++++++++++++++++++------------------------ 1 files changed, 41 insertions(+), 27 deletions(-) diff --git a/hw/ahci.c b/hw/ahci.c index a332a45..b6a81af 100644 --- a/hw/ahci.c +++ b/hw/ahci.c @@ -26,8 +26,15 @@ #include "dma.h" #include "cpu-common.h" #include -#define DPRINTF(...) +#define DEBUG_AHCI + +#ifdef DEBUG_AHCI +#define DPRINTF(fmt, ...) \ +do { printf("ahci: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) do {} while(0) +#endif enum { AHCI_PCI_BAR = 5, @@ -203,6 +210,8 @@ typedef struct ahci_control_regs { uint32_t version; } ahci_control_regs; +#define SATA_PORTS 4 + typedef struct ahci_port_regs { uint32_t lst_addr; uint32_t lst_addr_hi; @@ -240,7 +249,7 @@ typedef struct ahci_sg { typedef struct AHCIState{ ahci_control_regs control_regs; - ahci_port_regs port_regs[2]; + ahci_port_regs port_regs[SATA_PORTS]; int mem; QEMUTimer *timer; IDEBus *ide; @@ -268,8 +277,10 @@ static uint32_t ahci_port_read(AHCIState *s,int port,int offset) switch(offset) { case PORT_SCR: - if(s->ide && port==0) val=3; - else val=0; + if(s->ide && port==0) + val= 3 /* DET */ | (1 << 4) /* SPD */ | (1 << 8) /* IPM */; + else + val=0; break; case PORT_IRQ_STAT: val=pr->irq_stat; @@ -291,6 +302,7 @@ static uint32_t ahci_port_read(AHCIState *s,int port,int offset) val= p[offset>>2]; break; } + DPRINTF("ahci_port_read: port: 0x%x offset: 0x%x val: 0x%x\n", port, offset, val); return val; } @@ -299,7 +311,7 @@ static void ahci_check_irq(AHCIState *s) { ahci_port_regs *pr; int i; - for(i=0;i<2;i++) + for(i=0;iport_regs[i]; @@ -319,6 +331,7 @@ static void ahci_port_write(AHCIState *s,int port,int offset,uint32_t val) ahci_port_regs *pr=&s->port_regs[port]; uint32_t *p; + DPRINTF("ahci_port_write: port: 0x%x offset: 0x%x val: 0x%x\n", port, offset, val); switch(offset) { case PORT_LST_ADDR: @@ -396,7 +409,7 @@ static uint32_t ahci_mem_readl(void *ptr, target_phys_addr_t addr) val=p[addr>>2]; } } - else if(addr>=0x100 && addr<0x200) + else if(addr>=0x100 && addr<0x300) { val=ahci_port_read(s,(addr-0x100)>>7,addr&0x7f); } @@ -436,7 +449,7 @@ static void ahci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) p=(uint32_t *)&s->control_regs; } } - else if(addr>=0x100 && addr<0x200) + else if(addr>=0x100 && addr<0x300) { ahci_port_write(s,(addr-0x100)>>7,addr&0x7f,val); } @@ -459,10 +472,10 @@ static CPUWriteMemoryFunc *ahci_writefn[3]={ static void ahci_reg_init(AHCIState *s) { - s->control_regs.cap=2|(0x1f<<8); /*2 ports,32 cmd slot*/ - s->control_regs.ghc=1<<31; - s->control_regs.impl=1;/*2 ports*/ - s->control_regs.version=0x10100; + s->control_regs.cap = 3 | (0x1f << 8) | (1 << 20) ; /* 4 ports, 32 command slots, 1.5 Gb/s */ + s->control_regs.ghc = 1 << 31; /* AHCI Enable */ + s->control_regs.impl = 1; /* Port 0 implemented */ + s->control_regs.version = 0x10000; } static void padstr(char *str, const char *src, int len) @@ -619,19 +632,22 @@ static void handle_cmd(AHCIState *s,int port,int slot) prdt_num=cmd_hdr.opts>>16; if(prdt_num) cpu_physical_memory_read(cmd_hdr.tbl_addr+0x80,(uint8_t *)s->prdt_buf,prdt_num*32); - +#ifdef DEBUG_AHCI + DPRINTF("fis:"); for(i=0;iirq_stat |= (1<<2); break; default: - hw_error("unkonow command fis[0]=%02x fis[1]=%02x fis[2]=%02x\n",fis[0],fis[1],fis[2]);break; + hw_error("unknown command fis[0]=%02x fis[1]=%02x fis[2]=%02x\n",fis[0],fis[1],fis[2]);break; } } @@ -698,7 +714,7 @@ static void ahci_timer_function(void *opaque) AHCIState *s = opaque; ahci_port_regs *pr; int i,j; - for(i=0;i<2;i++) + for(i=0;iport_regs[i]; for(j=0;j<32 && pr->cmd_issue;j++) @@ -741,23 +757,21 @@ static void ahci_pci_map(PCIDevice *pci_dev, int region_num, #define PCI_VENDOR_MYDEVICE 0x8086 #define PCI_PRODUCT_MYDEVICE 0x2652 -#define PCI_CLASS_HEADERTYPE_00h 0x00 - static int pci_ahci_init(PCIDevice *dev) { struct ahci_pci_state *d; d = DO_UPCAST(struct ahci_pci_state, card, dev); pci_config_set_vendor_id(d->card.config,PCI_VENDOR_MYDEVICE); pci_config_set_device_id(d->card.config,PCI_PRODUCT_MYDEVICE); - d->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */ + d->card.config[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; d->card.config[PCI_CLASS_DEVICE] = 0; d->card.config[0x0b] = 1;//storage - d->card.config[0x0c] = 0x08; /* Cache line size */ - d->card.config[0x0d] = 0x40; /* Latency timer */ - d->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h; - d->card.config[0x3d] = 1; /* interrupt pin 0 */ + d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ + d->card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */ + d->card.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; + d->card.config[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */ - pci_register_bar(&d->card, 5, 0x200, + pci_register_bar(&d->card, 5, 0x400, PCI_BASE_ADDRESS_SPACE_MEMORY, ahci_pci_map); d->ahci=ahci_new(); d->ahci->irq = d->card.irq[0]; @@ -792,7 +806,7 @@ static int ahci_sysbus_init(SysBusDevice *dev) { ahci_sysbus_state *d = FROM_SYSBUS(ahci_sysbus_state, dev); d->ahci=ahci_new(); - sysbus_init_mmio(dev, 0x200, d->ahci->mem); + sysbus_init_mmio(dev, 0x400, d->ahci->mem); sysbus_init_irq(dev, &d->ahci->irq); return 0; }