From patchwork Sun May 2 09:50:51 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rabin Vincent X-Patchwork-Id: 51462 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A4818B7D60 for ; Sun, 2 May 2010 19:54:10 +1000 (EST) Received: from localhost ([127.0.0.1]:50637 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O8VsF-0003xU-SH for incoming@patchwork.ozlabs.org; Sun, 02 May 2010 05:54:07 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O8VoJ-0003F0-RZ for qemu-devel@nongnu.org; Sun, 02 May 2010 05:50:03 -0400 Received: from [140.186.70.92] (port=36352 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O8VoG-0003Eb-Kj for qemu-devel@nongnu.org; Sun, 02 May 2010 05:50:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O8VoE-0007qK-U9 for qemu-devel@nongnu.org; Sun, 02 May 2010 05:50:00 -0400 Received: from mail-pw0-f45.google.com ([209.85.160.45]:33475) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O8VoE-0007qA-PP for qemu-devel@nongnu.org; Sun, 02 May 2010 05:49:58 -0400 Received: by pwi6 with SMTP id 6so780217pwi.4 for ; Sun, 02 May 2010 02:49:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:cc:subject :date:message-id:x-mailer; bh=c1dIZarj5RGS7pSIA9K4otywTPva5zIzNxpc3YV9kF4=; b=ENmoKbD0GMlqLxkyMPdhQ05dOnD/fWi46R9i+E7hXSQBoYhovmCahVrPGiYNqkqS3Q st3RmcBw2P6DGoJd2rrLUjAYfNr/Ua8GtzcM6pWCyNrXK58BV+h6hmRr8jME3Mpx0aVi HM5GoD+o+LPE/7I9O5iRZRD34xGrS+Pyutx4U= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer; b=g7yIrVzZCbN7a1+oIw/AleLzEf6kIx1XFNdLaUpZC4A+tibkCDTiptpTXHvyJP6/M3 2O0K6LPXhtBLk/vo5MRCANAD+MhrhCyYex9eY/K1PS4RvgM/zikVtiYCIkCSp6mijQXs u5bXn5NUACtuhTC/sTPMECZskiQFyrujMAY/U= Received: by 10.115.39.40 with SMTP id r40mr9302619waj.183.1272793794639; Sun, 02 May 2010 02:49:54 -0700 (PDT) Received: from localhost.localdomain ([59.164.103.211]) by mx.google.com with ESMTPS id d20sm18519876waa.3.2010.05.02.02.49.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 02 May 2010 02:49:53 -0700 (PDT) From: Rabin Vincent To: qemu-devel@nongnu.org Date: Sun, 2 May 2010 15:20:51 +0530 Message-Id: <1272793852-26260-1-git-send-email-rabin@rab.in> X-Mailer: git-send-email 1.7.0.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: Rabin Vincent Subject: [Qemu-devel] [PATCH 1/2] arm_timer: reload timer when enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Reload the timer when TimerControl is written, if the timer is to be enabled. Otherwise, if an earlier write to TimerLoad was done while periodic mode was not set, s->delta may incorrectly still have the value of the maximum limit instead of the value written to TimerLoad. This problem is evident on versatileap on current linux-next, which enables TIMER_CTRL_32BIT before writing to TimerLoad and then enabling periodic mode and starting the timer. This causes the first periodic tick to be scheduled to occur after 0xffffffff periods, leading to a perceived hang while the kernel waits for the first timer tick. Signed-off-by: Rabin Vincent --- hw/arm_timer.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/hw/arm_timer.c b/hw/arm_timer.c index 9fef191..5b6947a 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -113,7 +113,7 @@ static void arm_timer_write(void *opaque, target_phys_addr_t offset, case 1: freq >>= 4; break; case 2: freq >>= 8; break; } - arm_timer_recalibrate(s, 0); + arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); ptimer_set_freq(s->timer, freq); if (s->control & TIMER_CTRL_ENABLE) { /* Restart the timer if still enabled. */