From patchwork Sat Apr 10 01:32:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 49882 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 82C6EB7CF6 for ; Sat, 10 Apr 2010 11:47:49 +1000 (EST) Received: from localhost ([127.0.0.1]:55688 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O0Pn1-0000TF-PR for incoming@patchwork.ozlabs.org; Fri, 09 Apr 2010 21:47:15 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O0PZf-0004a6-4E for qemu-devel@nongnu.org; Fri, 09 Apr 2010 21:33:27 -0400 Received: from [140.186.70.92] (port=49372 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O0PZa-0004Wt-8U for qemu-devel@nongnu.org; Fri, 09 Apr 2010 21:33:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O0PZW-0007Er-PC for qemu-devel@nongnu.org; Fri, 09 Apr 2010 21:33:22 -0400 Received: from hall.aurel32.net ([88.191.82.174]:35036) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O0PZW-0007EQ-Fh for qemu-devel@nongnu.org; Fri, 09 Apr 2010 21:33:18 -0400 Received: from [10.243.122.2] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1O0PZV-0005Me-66; Sat, 10 Apr 2010 03:33:17 +0200 Received: from aurel32 by volta.aurel32.net with local (Exim 4.71) (envelope-from ) id 1O0PZT-0004jd-6S; Sat, 10 Apr 2010 03:33:15 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 10 Apr 2010 03:32:50 +0200 Message-Id: <1270863186-10180-3-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1270863186-10180-1-git-send-email-aurelien@aurel32.net> References: <1270863186-10180-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Andrzej Zaborowski , Aurelien Jarno Subject: [Qemu-devel] [PATCH v2 02/18] tcg/arm: explicitely list clobbered/reserved regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Instead of writing very compact code, declare all registers that are clobbered or reserved one by one. This makes the code easier to read. Also declare all the 16 registers to TCG, and mark pc as reserved. Signed-off-by: Aurelien Jarno --- tcg/arm/tcg-target.c | 13 +++++++++---- tcg/arm/tcg-target.h | 3 ++- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index e86ed9a..35f6c47 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -39,6 +39,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { "%r12", "%r13", "%r14", + "%pc", }; #endif @@ -1580,15 +1581,19 @@ void tcg_target_init(TCGContext *s) tcg_abort(); #endif - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, - ((2 << TCG_REG_R14) - 1) & ~(1 << TCG_REG_R8)); + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); tcg_regset_set32(tcg_target_call_clobber_regs, 0, - ((2 << TCG_REG_R3) - 1) | - (1 << TCG_REG_R12) | (1 << TCG_REG_R14)); + (1 << TCG_REG_R0) | + (1 << TCG_REG_R1) | + (1 << TCG_REG_R2) | + (1 << TCG_REG_R3) | + (1 << TCG_REG_R12) | + (1 << TCG_REG_R14)); tcg_regset_clear(s->reserved_regs); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); tcg_add_target_add_op_defs(arm_op_defs); } diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 6d58de8..a0027b5 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -44,9 +44,10 @@ enum { TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, + TCG_REG_PC, }; -#define TCG_TARGET_NB_REGS 15 +#define TCG_TARGET_NB_REGS 16 #define TCG_CT_CONST_ARM 0x100