From patchwork Sat Apr 10 01:32:57 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 49886 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A7A4CB7CF6 for ; Sat, 10 Apr 2010 11:54:18 +1000 (EST) Received: from localhost ([127.0.0.1]:55719 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O0Ptn-000415-Tr for incoming@patchwork.ozlabs.org; Fri, 09 Apr 2010 21:54:15 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O0PZs-0004kG-ND for qemu-devel@nongnu.org; Fri, 09 Apr 2010 21:33:40 -0400 Received: from [140.186.70.92] (port=49461 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O0PZl-0004eL-Pv for qemu-devel@nongnu.org; Fri, 09 Apr 2010 21:33:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O0PZk-0007Hs-5O for qemu-devel@nongnu.org; Fri, 09 Apr 2010 21:33:33 -0400 Received: from hall.aurel32.net ([88.191.82.174]:35050) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O0PZj-0007Hg-V1 for qemu-devel@nongnu.org; Fri, 09 Apr 2010 21:33:32 -0400 Received: from [10.243.122.2] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1O0PZj-0005Mm-4a; Sat, 10 Apr 2010 03:33:31 +0200 Received: from aurel32 by volta.aurel32.net with local (Exim 4.71) (envelope-from ) id 1O0PZU-0004kT-5E; Sat, 10 Apr 2010 03:33:16 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 10 Apr 2010 03:32:57 +0200 Message-Id: <1270863186-10180-10-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1270863186-10180-1-git-send-email-aurelien@aurel32.net> References: <1270863186-10180-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Andrzej Zaborowski , Aurelien Jarno Subject: [Qemu-devel] [PATCH v2 09/18] tcg/arm: add rotation ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Aurelien Jarno --- tcg/arm/tcg-target.c | 19 +++++++++++++++++++ tcg/arm/tcg-target.h | 2 +- 2 files changed, 20 insertions(+), 1 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 7758601..b9a6abd 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1394,11 +1394,28 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_sar_i32: c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); + goto gen_shift32; + case INDEX_op_rotr_i32: + c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); /* Fall through. */ gen_shift32: tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); break; + case INDEX_op_rotl_i32: + if (const_args[2]) { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], + ((0x20 - args[2]) & 0x1f) ? + SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : + SHIFT_IMM_LSL(0)); + } else { + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_R8, args[1], 0x20); + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], + SHIFT_REG_ROR(TCG_REG_R8)); + } + break; + case INDEX_op_brcond_i32: if (const_args[1]) { int rot; @@ -1547,6 +1564,8 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_shl_i32, { "r", "r", "ri" } }, { INDEX_op_shr_i32, { "r", "r", "ri" } }, { INDEX_op_sar_i32, { "r", "r", "ri" } }, + { INDEX_op_rotl_i32, { "r", "r", "ri" } }, + { INDEX_op_rotr_i32, { "r", "r", "ri" } }, { INDEX_op_brcond_i32, { "r", "rI" } }, { INDEX_op_setcond_i32, { "r", "r", "rI" } }, diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 334edfa..bc08f91 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -66,7 +66,7 @@ enum { // #define TCG_TARGET_HAS_bswap32_i32 #define TCG_TARGET_HAS_not_i32 #define TCG_TARGET_HAS_neg_i32 -// #define TCG_TARGET_HAS_rot_i32 +#define TCG_TARGET_HAS_rot_i32 #define TCG_TARGET_HAS_andc_i32 // #define TCG_TARGET_HAS_orc_i32 // #define TCG_TARGET_HAS_eqv_i32