| Message ID | 1270662685-7379-18-git-send-email-aurelien@aurel32.net |
|---|---|
| State | New |
| Headers | show |
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 91542bd..03fe11c 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -65,10 +65,6 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { #endif static const int tcg_target_reg_alloc_order[] = { - TCG_REG_R0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, @@ -77,8 +73,12 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, - TCG_REG_R12, TCG_REG_R13, + TCG_REG_R0, + TCG_REG_R1, + TCG_REG_R2, + TCG_REG_R3, + TCG_REG_R12, TCG_REG_R14, };
The beginning of the register allocation order list on the TCG arm target matches the list of clobbered registers. This means that when an helper is called, there is almost always clobbered registers that have to be spilled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- tcg/arm/tcg-target.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-)