From patchwork Tue Dec 15 11:26:01 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 41181 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 57B35B7B6A for ; Tue, 15 Dec 2009 22:42:22 +1100 (EST) Received: from localhost ([127.0.0.1]:40708 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NKVnH-0006Be-DP for incoming@patchwork.ozlabs.org; Tue, 15 Dec 2009 06:42:19 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NKVY2-000193-E2 for qemu-devel@nongnu.org; Tue, 15 Dec 2009 06:26:34 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NKVXv-00014r-NE for qemu-devel@nongnu.org; Tue, 15 Dec 2009 06:26:31 -0500 Received: from [199.232.76.173] (port=43805 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NKVXu-00014F-SA for qemu-devel@nongnu.org; Tue, 15 Dec 2009 06:26:26 -0500 Received: from mail.valinux.co.jp ([210.128.90.3]:43010) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NKVXt-00059v-Tz for qemu-devel@nongnu.org; Tue, 15 Dec 2009 06:26:26 -0500 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id 143D9106A31; Tue, 15 Dec 2009 20:26:17 +0900 (JST) Received: (nullmailer pid 28235 invoked by uid 1000); Tue, 15 Dec 2009 11:26:07 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org, mst@redhat.com Date: Tue, 15 Dec 2009 20:26:01 +0900 Message-Id: <1260876367-28197-5-git-send-email-yamahata@valinux.co.jp> X-Mailer: git-send-email 1.6.5.4 In-Reply-To: <1260876367-28197-1-git-send-email-yamahata@valinux.co.jp> References: <1260876367-28197-1-git-send-email-yamahata@valinux.co.jp> X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: yamahata@valinux.co.jp Subject: [Qemu-devel] [PATCH V2 04/10] pci: use pci_regs.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org include pci_regs.h and remove duplicated defines. And remove unused PCI_REVISION and PCI_SUBDEVICE_ID. Signed-off-by: Isaku Yamahata Acked-by: Michael S. Tsirkin --- hw/pci.h | 77 ++----------------------------------------------------------- 1 files changed, 3 insertions(+), 74 deletions(-) diff --git a/hw/pci.h b/hw/pci.h index 3be7a99..b5e7abb 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -94,81 +94,10 @@ typedef struct PCIIORegion { #define PCI_ROM_SLOT 6 #define PCI_NUM_REGIONS 7 -/* Declarations from linux/pci_regs.h */ -#define PCI_VENDOR_ID 0x00 /* 16 bits */ -#define PCI_DEVICE_ID 0x02 /* 16 bits */ -#define PCI_COMMAND 0x04 /* 16 bits */ -#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ -#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ -#define PCI_COMMAND_MASTER 0x4 /* Enable bus master */ -#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ -#define PCI_STATUS 0x06 /* 16 bits */ -#define PCI_STATUS_INTERRUPT 0x08 -#define PCI_REVISION_ID 0x08 /* 8 bits */ -#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ -#define PCI_CLASS_DEVICE 0x0a /* Device class */ -#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ -#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ -#define PCI_HEADER_TYPE 0x0e /* 8 bits */ -#define PCI_HEADER_TYPE_NORMAL 0 -#define PCI_HEADER_TYPE_BRIDGE 1 -#define PCI_HEADER_TYPE_CARDBUS 2 +#include "pci_regs.h" + +/* PCI HEADER_TYPE */ #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 -#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ -#define PCI_BASE_ADDRESS_SPACE_IO 0x01 -#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 -#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ -#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ -#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ -#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ -#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ -#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ -#define PCI_IO_LIMIT 0x1d -#define PCI_IO_RANGE_TYPE_32 0x01 -#define PCI_IO_RANGE_MASK (~0x0fUL) -#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ -#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ -#define PCI_MEMORY_LIMIT 0x22 -#define PCI_MEMORY_RANGE_MASK (~0x0fUL) -#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ -#define PCI_PREF_MEMORY_LIMIT 0x26 -#define PCI_PREF_RANGE_MASK (~0x0fUL) -#define PCI_PREF_RANGE_TYPE_64 0x01 -#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ -#define PCI_PREF_LIMIT_UPPER32 0x2c -#define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */ -#define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */ -#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ -#define PCI_ROM_ADDRESS_ENABLE 0x01 -#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ -#define PCI_IO_LIMIT_UPPER16 0x32 -#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ -#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ -#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ -#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ -#define PCI_MIN_GNT 0x3e /* 8 bits */ -#define PCI_BRIDGE_CONTROL 0x3e -#define PCI_MAX_LAT 0x3f /* 8 bits */ - -/* Capability lists */ -#define PCI_CAP_LIST_ID 0 /* Capability ID */ -#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ - -#define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */ -#define PCI_SUBSYSTEM_VENDOR_ID 0x2c -#define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */ - -/* Bits in the PCI Status Register (PCI 2.3 spec) */ -#define PCI_STATUS_RESERVED1 0x007 -#define PCI_STATUS_INT_STATUS 0x008 -#define PCI_STATUS_CAP_LIST 0x010 -#define PCI_STATUS_66MHZ 0x020 -#define PCI_STATUS_RESERVED2 0x040 -#define PCI_STATUS_FAST_BACK 0x080 -#define PCI_STATUS_DEVSEL_MEDIUM 0x200 -#define PCI_STATUS_DEVSEL_SLOW 0x400 -#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ -#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \ PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \