From patchwork Fri Oct 30 12:21:11 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 37276 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 577BFB7C23 for ; Fri, 30 Oct 2009 23:33:54 +1100 (EST) Received: from localhost ([127.0.0.1]:60688 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N3qfv-0006Ks-Co for incoming@patchwork.ozlabs.org; Fri, 30 Oct 2009 08:33:51 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N3qVp-0001vL-Ri for qemu-devel@nongnu.org; Fri, 30 Oct 2009 08:23:26 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N3qVh-0001pG-WB for qemu-devel@nongnu.org; Fri, 30 Oct 2009 08:23:22 -0400 Received: from [199.232.76.173] (port=52361 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N3qVh-0001ov-Nk for qemu-devel@nongnu.org; Fri, 30 Oct 2009 08:23:17 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:34041) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1N3qVf-0002rP-7t for qemu-devel@nongnu.org; Fri, 30 Oct 2009 08:23:16 -0400 Received: from nm.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with ESMTP id 2B2DD1805F; Fri, 30 Oct 2009 21:23:05 +0900 (JST) Received: from yamahata by nm.local.valinux.co.jp with local (Exim 4.69) (envelope-from ) id 1N3qTv-0006dT-R5; Fri, 30 Oct 2009 21:21:27 +0900 From: Isaku Yamahata To: qemu-devel@nongnu.org, mst@redhat.com Date: Fri, 30 Oct 2009 21:21:11 +0900 Message-Id: <1256905286-25435-18-git-send-email-yamahata@valinux.co.jp> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1256905286-25435-1-git-send-email-yamahata@valinux.co.jp> References: <1256905286-25435-1-git-send-email-yamahata@valinux.co.jp> X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: yamahata@valinux.co.jp Subject: [Qemu-devel] [PATCH V6 17/32] pci: 64bit bar support. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org implemented pci 64bit bar support. The tricky bit is pci_update_mapping(). An OS is allowed to set the BAR such that OS can't address the area pointed by BAR. It doesn't make sense, though. In that case, don't map the BAR. Signed-off-by: Isaku Yamahata --- hw/pci.c | 35 ++++++++++++++++++++++++++++++----- hw/pci.h | 1 + 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index b462bd6..7da3db9 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -484,8 +484,14 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, wmask |= PCI_ROM_ADDRESS_ENABLE; } pci_set_long(pci_dev->config + addr, type); - pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); - pci_set_long(pci_dev->cmask + addr, 0xffffffff); + if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && + r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { + pci_set_quad(pci_dev->wmask + addr, wmask); + pci_set_quad(pci_dev->cmask + addr, ~0ULL); + } else { + pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); + pci_set_long(pci_dev->cmask + addr, 0xffffffff); + } } static void pci_update_mappings(PCIDevice *d) @@ -513,7 +519,11 @@ static void pci_update_mappings(PCIDevice *d) } } else { if (cmd & PCI_COMMAND_MEMORY) { - new_addr = pci_get_long(d->config + pci_bar(d, i)); + if (r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { + new_addr = pci_get_quad(d->config + pci_bar(d, i)); + } else { + new_addr = pci_get_long(d->config + pci_bar(d, i)); + } /* the ROM slot has a specific enable bit */ if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) goto no_mem_map; @@ -531,7 +541,15 @@ static void pci_update_mappings(PCIDevice *d) * Without this, PC ide doesn't work well. * TODO: remove this work around. */ - last_addr >= UINT32_MAX) { + (!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) && + last_addr >= UINT32_MAX) || + + /* + * OS is allowed to set BAR beyond its addressable + * bits. For example, 32 bit OS can set 64bit bar + * to >4G. Check it. + */ + last_addr >= TARGET_PHYS_ADDR_MAX) { new_addr = PCI_BAR_UNMAPPED; } } else { @@ -773,8 +791,15 @@ static void pci_info_device(PCIDevice *d) " [0x%04"FMT_PCIBUS"].\n", r->addr, r->addr + r->size - 1); } else { - monitor_printf(mon, "32 bit memory at 0x%08"FMT_PCIBUS + const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ? + "64 bit" : "32 bit"; + const char *prefetch = + r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ? + " prefetchable" : ""; + + monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS " [0x%08"FMT_PCIBUS"].\n", + type, prefetch, r->addr, r->addr + r->size - 1); } } diff --git a/hw/pci.h b/hw/pci.h index 305c030..e83faf5 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -114,6 +114,7 @@ typedef struct PCIIORegion { #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ #define PCI_BASE_ADDRESS_SPACE_IO 0x01 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 +#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */