From patchwork Tue Oct 27 08:46:12 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Juha.Riihimaki@nokia.com X-Patchwork-Id: 36968 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E80A0B7C1F for ; Tue, 27 Oct 2009 19:48:01 +1100 (EST) Received: from localhost ([127.0.0.1]:42965 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N2hif-0003Pq-Pg for incoming@patchwork.ozlabs.org; Tue, 27 Oct 2009 04:47:57 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N2hhD-0002zJ-9B for qemu-devel@nongnu.org; Tue, 27 Oct 2009 04:46:27 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N2hh8-0002xF-3t for qemu-devel@nongnu.org; Tue, 27 Oct 2009 04:46:26 -0400 Received: from [199.232.76.173] (port=60943 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N2hh7-0002x7-Ss for qemu-devel@nongnu.org; Tue, 27 Oct 2009 04:46:21 -0400 Received: from smtp.nokia.com ([192.100.122.233]:47590 helo=mgw-mx06.nokia.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1N2hh7-00016G-75 for qemu-devel@nongnu.org; Tue, 27 Oct 2009 04:46:21 -0400 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9R8jkec024323 for ; Tue, 27 Oct 2009 10:46:14 +0200 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Oct 2009 10:46:12 +0200 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Oct 2009 10:46:12 +0200 Received: from localhost.localdomain (esdhcp041124.research.nokia.com [172.21.41.124]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9R8kAH8027370 for ; Tue, 27 Oct 2009 10:46:11 +0200 From: juha.riihimaki@nokia.com To: qemu-devel@nongnu.org Date: Tue, 27 Oct 2009 10:46:12 +0200 Message-Id: <1256633172-10636-1-git-send-email-juha.riihimaki@nokia.com> X-Mailer: git-send-email 1.6.5 MIME-Version: 1.0 X-OriginalArrivalTime: 27 Oct 2009 08:46:12.0537 (UTC) FILETIME=[EFDD5290:01CA56E1] X-Nokia-AV: Clean X-MIME-Autoconverted: from 8bit to quoted-printable by mgw-mx06.nokia.com id n9R8jkec024323 X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 1) Subject: [Qemu-devel] [PATCH v3] target-arm: optimize arm load/store multiple ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Juha Riihimäki ARM load/store multiple instructions can be slightly optimized by loading the register offset constant into a variable outside the register loop and using the preloaded variable inside the loop instead of reloading the offset value to a temporary variable on each loop iteration. This causes less TCG ops to be generated for a ARM load/ store multiple instruction if there are more than one register accessed, otherwise the number of generated TCG ops is the same. This patch has been revised to apply against the latest git where tmp2 is already used inside the optimized loop so we use tmp3 for the new temporary constant value. Signed-off-by: Juha Riihimäki --- target-arm/translate.c | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 1988cc6..24fb9d2 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6824,6 +6824,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } rn = (insn >> 16) & 0xf; addr = load_reg(s, rn); + tmp3 = tcg_const_i32(4); /* compute total size */ loaded_base = 0; @@ -6837,7 +6838,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) if (insn & (1 << 23)) { if (insn & (1 << 24)) { /* pre increment */ - tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_add_i32(addr, addr, tmp3); } else { /* post increment */ } @@ -6890,7 +6891,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) j++; /* no need to add after the last transfer */ if (j != n) - tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_add_i32(addr, addr, tmp3); } } if (insn & (1 << 21)) { @@ -6900,7 +6901,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) /* pre increment */ } else { /* post increment */ - tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_add_i32(addr, addr, tmp3); } } else { if (insn & (1 << 24)) { @@ -6916,6 +6917,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } else { dead_tmp(addr); } + tcg_temp_free_i32(tmp3); if (loaded_base) { store_reg(s, rn, loaded_var); }