From patchwork Sat Oct 24 12:19:06 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Juha.Riihimaki@nokia.com X-Patchwork-Id: 36835 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DFAF6B7BC7 for ; Sat, 24 Oct 2009 23:31:14 +1100 (EST) Received: from localhost ([127.0.0.1]:54904 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N1fm4-00051i-6I for incoming@patchwork.ozlabs.org; Sat, 24 Oct 2009 08:31:12 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N1fan-0008I9-7g for qemu-devel@nongnu.org; Sat, 24 Oct 2009 08:19:33 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N1faf-0008DA-RJ for qemu-devel@nongnu.org; Sat, 24 Oct 2009 08:19:30 -0400 Received: from [199.232.76.173] (port=58455 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N1faf-0008D4-1s for qemu-devel@nongnu.org; Sat, 24 Oct 2009 08:19:25 -0400 Received: from smtp.nokia.com ([192.100.122.230]:58024 helo=mgw-mx03.nokia.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1N1fae-0004II-G6 for qemu-devel@nongnu.org; Sat, 24 Oct 2009 08:19:24 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9OCJH3I011602 for ; Sat, 24 Oct 2009 15:19:21 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Sat, 24 Oct 2009 15:19:19 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Sat, 24 Oct 2009 15:19:18 +0300 Received: from localhost.localdomain (essapo-nirac252105.europe.nokia.com [10.162.252.105]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9OCJ8qD022164 for ; Sat, 24 Oct 2009 15:19:17 +0300 From: juha.riihimaki@nokia.com To: qemu-devel@nongnu.org Date: Sat, 24 Oct 2009 15:19:06 +0300 Message-Id: <1256386749-85299-8-git-send-email-juha.riihimaki@nokia.com> X-Mailer: git-send-email 1.6.5 In-Reply-To: <1256386749-85299-1-git-send-email-juha.riihimaki@nokia.com> References: <1256386749-85299-1-git-send-email-juha.riihimaki@nokia.com> MIME-Version: 1.0 X-OriginalArrivalTime: 24 Oct 2009 12:19:18.0801 (UTC) FILETIME=[35D52010:01CA54A4] X-Nokia-AV: Clean X-MIME-Autoconverted: from 8bit to quoted-printable by mgw-mx03.nokia.com id n9OCJH3I011602 X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 1) Subject: [Qemu-devel] [PATCH v2 07/10] target-arm: optimize thumb2 load/store multiple ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Juha Riihimäki Thumb2 load/store multiple instructions can be slightly optimized by loading the register offset constant into a variable outside the register loop and using the preloaded variable inside the loop instead of reloading the offset value to a temporary variable on each loop iteration. This causes less TCG ops to be generated for a Thumb2 load/ store multiple instruction if there are more than one register accessed, otherwise the amount of generated TCG ops will be the same. Signed-off-by: Juha Riihimäki Acked-by: Laurent Desnogues --- target-arm/translate.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 9e924d4..353f638 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7374,6 +7374,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) tcg_gen_addi_i32(addr, addr, -offset); } + tmp2 = tcg_const_i32(4); for (i = 0; i < 16; i++) { if ((insn & (1 << i)) == 0) continue; @@ -7390,8 +7391,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) tmp = load_reg(s, i); gen_st32(tmp, addr, IS_USER(s)); } - tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_add_i32(addr, addr, tmp2); } + tcg_temp_free_i32(tmp2); if (insn & (1 << 21)) { /* Base register writeback. */ if (insn & (1 << 24)) {