From patchwork Sat Oct 24 12:19:04 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Juha.Riihimaki@nokia.com X-Patchwork-Id: 36834 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EA2F2B7BCE for ; Sat, 24 Oct 2009 23:28:45 +1100 (EST) Received: from localhost ([127.0.0.1]:53698 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N1fjf-0003Zv-3L for incoming@patchwork.ozlabs.org; Sat, 24 Oct 2009 08:28:43 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N1fam-0008H9-7I for qemu-devel@nongnu.org; Sat, 24 Oct 2009 08:19:32 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N1fad-0008BF-4P for qemu-devel@nongnu.org; Sat, 24 Oct 2009 08:19:28 -0400 Received: from [199.232.76.173] (port=58453 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N1fac-0008B4-B9 for qemu-devel@nongnu.org; Sat, 24 Oct 2009 08:19:22 -0400 Received: from smtp.nokia.com ([192.100.122.230]:58018 helo=mgw-mx03.nokia.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1N1faa-0004HS-LR for qemu-devel@nongnu.org; Sat, 24 Oct 2009 08:19:21 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9OCJGW3011600 for ; Sat, 24 Oct 2009 15:19:17 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Sat, 24 Oct 2009 15:19:16 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Sat, 24 Oct 2009 15:19:16 +0300 Received: from localhost.localdomain (essapo-nirac252105.europe.nokia.com [10.162.252.105]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9OCJ8qB022164 for ; Sat, 24 Oct 2009 15:19:15 +0300 From: juha.riihimaki@nokia.com To: qemu-devel@nongnu.org Date: Sat, 24 Oct 2009 15:19:04 +0300 Message-Id: <1256386749-85299-6-git-send-email-juha.riihimaki@nokia.com> X-Mailer: git-send-email 1.6.5 In-Reply-To: <1256386749-85299-1-git-send-email-juha.riihimaki@nokia.com> References: <1256386749-85299-1-git-send-email-juha.riihimaki@nokia.com> MIME-Version: 1.0 X-OriginalArrivalTime: 24 Oct 2009 12:19:16.0281 (UTC) FILETIME=[34549A90:01CA54A4] X-Nokia-AV: Clean X-MIME-Autoconverted: from 8bit to quoted-printable by mgw-mx03.nokia.com id n9OCJGW3011600 X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 1) Subject: [Qemu-devel] [PATCH v2 05/10] target-arm: optimize arm load/store multiple ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Juha Riihimäki RM load/store multiple instructions can be slightly optimized by loading the register offset constant into a variable outside the register loop and using the preloaded variable inside the loop instead of reloading the offset value to a temporary variable on each loop iteration. This causes less TCG ops to be generated for a ARM load/ store multiple instruction if there are more than one register accessed, otherwise the number of generated TCG ops is the same. Signed-off-by: Juha Riihimäki Acked-by: Laurent Desnogues --- target-arm/translate.c | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 38fb833..d1e2ed2 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6852,6 +6852,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } rn = (insn >> 16) & 0xf; addr = load_reg(s, rn); + tmp2 = tcg_const_i32(4); /* compute total size */ loaded_base = 0; @@ -6865,7 +6866,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) if (insn & (1 << 23)) { if (insn & (1 << 24)) { /* pre increment */ - tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_add_i32(addr, addr, tmp2); } else { /* post increment */ } @@ -6918,7 +6919,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) j++; /* no need to add after the last transfer */ if (j != n) - tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_add_i32(addr, addr, tmp2); } } if (insn & (1 << 21)) { @@ -6928,7 +6929,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) /* pre increment */ } else { /* post increment */ - tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_add_i32(addr, addr, tmp2); } } else { if (insn & (1 << 24)) { @@ -6944,6 +6945,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } else { dead_tmp(addr); } + tcg_temp_free_i32(tmp2); if (loaded_base) { store_reg(s, rn, loaded_var); }