From patchwork Fri Oct 9 06:28:52 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 35577 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8BA65B7B83 for ; Fri, 9 Oct 2009 18:36:22 +1100 (EST) Received: from localhost ([127.0.0.1]:50793 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MwA1T-00068w-7k for incoming@patchwork.ozlabs.org; Fri, 09 Oct 2009 03:36:19 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Mw9On-0001j8-R0 for qemu-devel@nongnu.org; Fri, 09 Oct 2009 02:56:22 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Mw9Oj-0001ev-95 for qemu-devel@nongnu.org; Fri, 09 Oct 2009 02:56:21 -0400 Received: from [199.232.76.173] (port=47778 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Mw9Oi-0001eo-QC for qemu-devel@nongnu.org; Fri, 09 Oct 2009 02:56:16 -0400 Received: from mx20.gnu.org ([199.232.41.8]:7648) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Mw9Oi-0004Nx-69 for qemu-devel@nongnu.org; Fri, 09 Oct 2009 02:56:16 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Mw9Og-0008AC-TX for qemu-devel@nongnu.org; Fri, 09 Oct 2009 02:56:15 -0400 Received: from nm.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with ESMTP id 2C40349E26; Fri, 9 Oct 2009 15:30:40 +0900 (JST) Received: from yamahata by nm.local.valinux.co.jp with local (Exim 4.69) (envelope-from ) id 1Mw8yN-00046w-10; Fri, 09 Oct 2009 15:29:03 +0900 From: Isaku Yamahata To: qemu-devel@nongnu.org, mst@redhat.com Date: Fri, 9 Oct 2009 15:28:52 +0900 Message-Id: <1255069742-15724-20-git-send-email-yamahata@valinux.co.jp> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1255069742-15724-1-git-send-email-yamahata@valinux.co.jp> References: <1255069742-15724-1-git-send-email-yamahata@valinux.co.jp> X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by mx20.gnu.org: GNU/Linux 2.6 (newer, 3) X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) Cc: yamahata@valinux.co.jp Subject: [Qemu-devel] [PATCH V5 19/29] pci: split out ioport address parsing from pci configuration access logic. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Split out pci_data_{write, read} into two part, one is the code which convert ioport address into pci device and the other is the code which access PCI configuration space. Later PCI express code will use the access code. PCI express addressing scheme is different so that the address must be parsed differently. PCI: 0- 7 bit: offset in the configuration space (256bytes) 7-15 bit: devfn 16-24 bit: bus PCI express: 0-11 bit: offset in the configuration space (4KBytes) 12-19 bit: devfn 20-28 bit: bus Signed-off-by: Isaku Yamahata --- hw/pci.c | 80 ++++++++++++++++++++++++++++++------------------------------- 1 files changed, 39 insertions(+), 41 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index 0021c96..d472b58 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -654,46 +654,24 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) pci_update_mappings(d); } -static inline PCIDevice *pci_addr_to_dev(PCIBus *bus, uint32_t addr) -{ - uint8_t bus_num = (addr >> 16) & 0xff; - uint8_t devfn = (addr >> 8) & 0xff; - return pci_find_device(bus, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn)); -} - -static inline int pci_addr_to_config(uint32_t addr) -{ - return addr & 0xff; -} - -void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) +static void pci_dev_write_config(PCIDevice *pci_dev, + uint32_t config_addr, uint32_t val, int len) { - PCIBus *s = opaque; - PCIDevice *pci_dev; - int config_addr; - -#if 0 - PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n", - addr, val, len); -#endif - pci_dev = pci_addr_to_dev(s, addr); + assert(len == 1 || len == 2 || len == 4); if (!pci_dev) return; - config_addr = addr & 0xff; - config_addr = pci_addr_to_config(addr); - PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n", - pci_dev->name, config_addr, val, len); + + PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRI32x" len=%d\n", + __func__, pci_dev->name, config_addr, val, len); pci_dev->config_write(pci_dev, config_addr, val, len); } -uint32_t pci_data_read(void *opaque, uint32_t addr, int len) +static uint32_t pci_dev_read_config(PCIDevice *pci_dev, + uint32_t config_addr, int len) { - PCIBus *s = opaque; - PCIDevice *pci_dev; - int config_addr; uint32_t val; - pci_dev = pci_addr_to_dev(s, addr); + assert(len == 1 || len == 2 || len == 4); if (!pci_dev) { switch(len) { case 1: @@ -707,20 +685,40 @@ uint32_t pci_data_read(void *opaque, uint32_t addr, int len) val = 0xffffffff; break; } - goto the_end; + } else { + val = pci_dev->config_read(pci_dev, config_addr, len); + PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n", + __func__, pci_dev->name, config_addr, val, len); } - config_addr = pci_addr_to_config(addr); - val = pci_dev->config_read(pci_dev, config_addr, len); - PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n", - pci_dev->name, config_addr, val, len); - the_end: -#if 0 - PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n", - addr, val, len); -#endif return val; } +static inline PCIDevice *pci_addr_to_dev(PCIBus *bus, uint32_t addr) +{ + uint8_t bus_num = (addr >> 16) & 0xff; + uint8_t devfn = (addr >> 8) & 0xff; + return pci_find_device(bus, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn)); +} + +static inline int pci_addr_to_config(uint32_t addr) +{ + return addr & 0xff; +} + +void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) +{ + PCIBus *s = opaque; + pci_dev_write_config(pci_addr_to_dev(s, addr), pci_addr_to_config(addr), + val, len); +} + +uint32_t pci_data_read(void *opaque, uint32_t addr, int len) +{ + PCIBus *s = opaque; + return pci_dev_read_config(pci_addr_to_dev(s, addr), + pci_addr_to_config(addr), len); +} + /***********************************************************/ /* generic PCI irq support */