From patchwork Mon Oct 5 10:06:52 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 34965 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CCC4BB7B97 for ; Mon, 5 Oct 2009 21:10:23 +1100 (EST) Received: from localhost ([127.0.0.1]:34628 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MukWJ-0001HF-NC for incoming@patchwork.ozlabs.org; Mon, 05 Oct 2009 06:10:19 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MukV8-0001E5-IR for qemu-devel@nongnu.org; Mon, 05 Oct 2009 06:09:07 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MukUv-00014g-Sz for qemu-devel@nongnu.org; Mon, 05 Oct 2009 06:08:59 -0400 Received: from [199.232.76.173] (port=44776 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MukUv-00013i-J7 for qemu-devel@nongnu.org; Mon, 05 Oct 2009 06:08:53 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:55411) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MukUu-00076Y-8c for qemu-devel@nongnu.org; Mon, 05 Oct 2009 06:08:52 -0400 Received: from nm.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with ESMTP id ED17949D88; Mon, 5 Oct 2009 19:08:41 +0900 (JST) Received: from yamahata by nm.local.valinux.co.jp with local (Exim 4.69) (envelope-from ) id 1MukT9-0004D2-VU; Mon, 05 Oct 2009 19:07:03 +0900 From: Isaku Yamahata To: qemu-devel@nongnu.org, mst@redhat.com Date: Mon, 5 Oct 2009 19:06:52 +0900 Message-Id: <1254737223-16129-13-git-send-email-yamahata@valinux.co.jp> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1254737223-16129-1-git-send-email-yamahata@valinux.co.jp> References: <1254737223-16129-1-git-send-email-yamahata@valinux.co.jp> X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: yamahata@valinux.co.jp Subject: [Qemu-devel] [PATCH 12/23] pci: 64bit bar support. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org implemented pci 64bit bar support. Signed-off-by: Isaku Yamahata --- hw/pci.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++-------- hw/pci.h | 2 ++ 2 files changed, 48 insertions(+), 8 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index 21565f5..09a6816 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -395,6 +395,13 @@ int pci_unregister_device(PCIDevice *pci_dev) return 0; } +static inline int pci_bar_is_mem64(const PCIIORegion *r) +{ + return !(r->type & PCI_ADDRESS_SPACE_IO) && + (r->type & PCI_ADDRESS_SPACE_MEM_TYPE_MASK) == + PCI_ADDRESS_SPACE_MEM_TYPE_64; +} + void pci_register_bar(PCIDevice *pci_dev, int region_num, pcibus_t size, int type, PCIMapIORegionFunc *map_func) @@ -427,8 +434,13 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, addr = 0x10 + region_num * 4; } pci_set_long(pci_dev->config + addr, type); - pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); - pci_set_long(pci_dev->cmask + addr, 0xffffffff); + if (pci_bar_is_mem64(r)) { + pci_set_quad(pci_dev->wmask + addr, wmask); + pci_set_quad(pci_dev->cmask + addr, ~0ULL); + } else { + pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); + pci_set_long(pci_dev->cmask + addr, 0xffffffff); + } } static void pci_update_mappings(PCIDevice *d) @@ -462,7 +474,11 @@ static void pci_update_mappings(PCIDevice *d) } } else { if (cmd & PCI_COMMAND_MEMORY) { - new_addr = pci_get_long(d->config + config_ofs); + if (pci_bar_is_mem64(r)) { + new_addr = pci_get_quad(d->config + config_ofs); + } else { + new_addr = pci_get_long(d->config + config_ofs); + } /* the ROM slot has a specific enable bit */ if (i == PCI_ROM_SLOT && !(new_addr & 1)) goto no_mem_map; @@ -473,11 +489,24 @@ static void pci_update_mappings(PCIDevice *d) mappings, we handle specific values as invalid mappings. */ if (last_addr <= new_addr || new_addr == 0 || - last_addr == PCI_BAR_UNMAPPED || + last_addr == PCI_BAR_UNMAPPED) { + new_addr = PCI_BAR_UNMAPPED; + } - /* keep old behaviour - * without this, PC ide doesn't work well. */ - last_addr >= UINT32_MAX) { + /* + * work around: without this, PC ide and other devices + * don't work well. + * OS writes all 1 bits to 32 BAR to find its size + * resulting in setting UINT32_MAX - alignemnt, + * and then OS sets the BAR to where they really want + * the BAR to sit. + * On the other hand, there are some important areas + * blow 4G on i386/x86_64. So setting BAR over those area + * below 4G causes troubles. + * We work around the issues by prohibitting BAR + * from sitting right blow 4G. + */ + if (!pci_bar_is_mem64(r) && last_addr >= UINT32_MAX) { new_addr = PCI_BAR_UNMAPPED; } } else { @@ -736,7 +765,16 @@ static void pci_info_device(PCIDevice *d) monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS" [0x%04"FMT_PCIBUS"].\n", r->addr, r->addr + r->size - 1); } else { - monitor_printf(mon, "32 bit memory at 0x%08"FMT_PCIBUS" [0x%08"FMT_PCIBUS"].\n", + const char *type = pci_bar_is_mem64(r)? "64 bit": "32 bit"; + const char *prefetch = ""; + + if (r->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) { + prefetch = " prefetchable"; + } + + monitor_printf(mon, "%s%s memory at " + "0x%08"FMT_PCIBUS" [0x%08"FMT_PCIBUS"].\n", + type, prefetch, r->addr, r->addr + r->size - 1); } } diff --git a/hw/pci.h b/hw/pci.h index cbf80c0..b65ce03 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -84,6 +84,8 @@ typedef int PCIUnregisterFunc(PCIDevice *pci_dev); #define PCI_ADDRESS_SPACE_MEM 0x00 #define PCI_ADDRESS_SPACE_IO 0x01 +#define PCI_ADDRESS_SPACE_MEM_TYPE_MASK 0x06 +#define PCI_ADDRESS_SPACE_MEM_TYPE_64 0x04 /* 64 bit address */ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 typedef struct PCIIORegion {