diff mbox

[v1,1/3] xilinx_axienet: Implement R_IS behaviour

Message ID 0726bd9390d5c58e61657ac42f368ecebc6cc1c3.1354690179.git.peter.crosthwaite@xilinx.com
State New
Headers show

Commit Message

Peter Crosthwaite Dec. 5, 2012, 6:53 a.m. UTC 
The interrupt status register R_IS is the standard clear-on-write behaviour.
This was unimplemented and defaulting to updating the register to the written
value. Implemented clear-on-write.

Reported-by: Jason Wu <huanyu@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 hw/xilinx_axienet.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)
diff mbox

Patch

diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
index baae02b..f2e3bf1 100644
--- a/hw/xilinx_axienet.c
+++ b/hw/xilinx_axienet.c
@@ -591,6 +591,10 @@  static void enet_write(void *opaque, hwaddr addr,
             s->maddr[s->fmi & 3][addr & 1] = value;
             break;
 
+        case R_IS:
+            s->regs[addr] &= ~value;
+            break;
+
         case 0x8000 ... 0x83ff:
             s->ext_mtable[addr - 0x8000] = value;
             break;