From patchwork Thu Feb 3 14:55:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 81671 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 25B43B7124 for ; Fri, 4 Feb 2011 02:01:35 +1100 (EST) Received: from localhost ([127.0.0.1]:50554 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pl0ge-0008If-7M for incoming@patchwork.ozlabs.org; Thu, 03 Feb 2011 10:01:32 -0500 Received: from [140.186.70.92] (port=57781 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pl0b6-0005iZ-8m for qemu-devel@nongnu.org; Thu, 03 Feb 2011 09:55:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pl0ax-0000xa-EN for qemu-devel@nongnu.org; Thu, 03 Feb 2011 09:55:48 -0500 Received: from david.siemens.de ([192.35.17.14]:22695) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pl0ax-0000ww-0V for qemu-devel@nongnu.org; Thu, 03 Feb 2011 09:55:39 -0500 Received: from mail1.siemens.de (localhost [127.0.0.1]) by david.siemens.de (8.13.6/8.13.6) with ESMTP id p13Etaan001970; Thu, 3 Feb 2011 15:55:36 +0100 Received: from mchn199C.mchp.siemens.de ([139.25.109.49]) by mail1.siemens.de (8.13.6/8.13.6) with ESMTP id p13Eta0w010597; Thu, 3 Feb 2011 15:55:36 +0100 From: Jan Kiszka To: qemu-devel@nongnu.org, Anthony Liguori Date: Thu, 3 Feb 2011 15:55:34 +0100 Message-Id: <0072079efad1c31da849cff7ad2cb426aeb6c29f.1296744934.git.jan.kiszka@siemens.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 192.35.17.14 Cc: Gleb Natapov , Marcelo Tosatti , Alexander Graf , kvm@vger.kernel.org, Avi Kivity Subject: [Qemu-devel] [0.14?][PATCH 3/4] ioapic: Prepare for base address relocation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The registers of real IOAPICs can be relocated during runtime (via chipset registers). We don't support this yet, but qemu-kvm carries the current base address in its version 2 vmstate. To align both implementations for migratability, add the proper infrastructure to accept initial as well as updated base addresses and include the current address in the vmstate. This is done in a way that will also allow multiple IOAPICs in the future. Signed-off-by: Jan Kiszka --- hw/ioapic.c | 17 +++++++++++++++++ hw/ioapic.h | 4 ++++ hw/pc_piix.c | 5 ++--- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/hw/ioapic.c b/hw/ioapic.c index c7019f5..b53d436 100644 --- a/hw/ioapic.c +++ b/hw/ioapic.c @@ -63,6 +63,8 @@ struct IOAPICState { uint32_t irr; uint64_t ioredtbl[IOAPIC_NUM_PINS]; + uint64_t default_base_address; + uint64_t current_base_address; }; static IOAPICState *ioapics[MAX_IOAPICS]; @@ -237,6 +239,7 @@ static int ioapic_pre_load(void *opaque) /* in case we are loading version 1, set these to sane values */ s->irr = 0; + s->current_base_address = s->default_base_address; return 0; } @@ -249,6 +252,7 @@ static const VMStateDescription vmstate_ioapic = { .fields = (VMStateField []) { VMSTATE_UINT8(id, IOAPICState), VMSTATE_UINT8(ioregsel, IOAPICState), + VMSTATE_UINT64_V(current_base_address, IOAPICState, 2), VMSTATE_UINT32_V(irr, IOAPICState, 2), VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS), VMSTATE_END_OF_LIST() @@ -260,6 +264,8 @@ static void ioapic_reset(DeviceState *d) IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d); int i; + s->current_base_address = s->default_base_address; + sysbus_mmio_map(&s->busdev, 0, s->current_base_address); s->id = 0; s->ioregsel = 0; s->irr = 0; @@ -279,6 +285,17 @@ static CPUWriteMemoryFunc * const ioapic_mem_write[3] = { ioapic_mem_writel, }; +void ioapic_set_base_address(DeviceState *d, target_phys_addr_t addr) +{ + IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d); + + s->current_base_address = addr; + if (!s->default_base_address) { + s->default_base_address = addr; + } + sysbus_mmio_map(&s->busdev, 0, addr); +} + static int ioapic_init1(SysBusDevice *dev) { IOAPICState *s = FROM_SYSBUS(IOAPICState, dev); diff --git a/hw/ioapic.h b/hw/ioapic.h index c441567..1130d60 100644 --- a/hw/ioapic.h +++ b/hw/ioapic.h @@ -17,4 +17,8 @@ * License along with this library; if not, see . */ +#define IOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000 + void ioapic_eio_broadcast(int vector); + +void ioapic_set_base_address(DeviceState *d, target_phys_addr_t addr); diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 7b74473..479334f 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -25,6 +25,7 @@ #include "hw.h" #include "pc.h" #include "apic.h" +#include "ioapic.h" #include "pci.h" #include "usb-uhci.h" #include "usb-ohci.h" @@ -46,13 +47,11 @@ static const int ide_irq[MAX_IDE_BUS] = { 14, 15 }; static void ioapic_init(IsaIrqState *isa_irq_state) { DeviceState *dev; - SysBusDevice *d; unsigned int i; dev = qdev_create(NULL, "ioapic"); qdev_init_nofail(dev); - d = sysbus_from_qdev(dev); - sysbus_mmio_map(d, 0, 0xfec00000); + ioapic_set_base_address(dev, IOAPIC_DEFAULT_BASE_ADDRESS); for (i = 0; i < IOAPIC_NUM_PINS; i++) { isa_irq_state->ioapic[i] = qdev_get_gpio_in(dev, i);