Show patches with: Submitter = Fea Wang       |    State = Action Required       |    Archived = No       |   19 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[4/4] hw/net: Fix the transmission return size hw/dma: Add error handling for loading descriptions failing - - - - --- 2024-06-03 Fea Wang New
[3/4] hw/dma: Add a trace log for a description loading failure hw/dma: Add error handling for loading descriptions failing - - - - --- 2024-06-03 Fea Wang New
[2/4] hw/dma: Break the loop when loading descriptions fails hw/dma: Add error handling for loading descriptions failing - - - - --- 2024-06-03 Fea Wang New
[1/4] hw/dma: Enhance error handling in loading description hw/dma: Add error handling for loading descriptions failing - - - - --- 2024-06-03 Fea Wang New
[RESEND,v2,5/5] target/riscv: Reserve exception codes for sw-check and hw-err target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-15 Fea Wang New
[RESEND,v2,4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-15 Fea Wang New
[RESEND,v2,3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-05-15 Fea Wang New
[RESEND,v2,2/5] target/riscv: Support the version for ss1p13 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-05-15 Fea Wang New
[RESEND,v2,1/5] target/riscv: Reuse the conversion function of priv_spec target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-15 Fea Wang New
[5/5] target/riscv: Reserve exception codes for sw-check and hw-err target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-15 Fea Wang New
[4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-15 Fea Wang New
[3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-15 Fea Wang New
[2/5] target/riscv: Support the version for ss1p13 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-05-15 Fea Wang New
[1/5] target/riscv: Reuse the conversion function of priv_spec target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-15 Fea Wang New
[5/5] target/riscv: Reserve exception codes for sw-check and hw-err target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-10 Fea Wang New
[4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-10 Fea Wang New
[3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-10 Fea Wang New
[2/5] target/riscv: Support the version for ss1p13 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-05-10 Fea Wang New
[1/5] target/riscv: Reuse the conversion function of priv_spec and string target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-10 Fea Wang New