Show patches with: Submitter = Himanshu Chauhan       |    State = Action Required       |    Archived = No       |   24 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v7,4/4] target/riscv: Enable sdtrig for Ventana's Veyron CPUs Introduce sdtrig ISA extension - - - - --- 2024-03-14 Himanshu Chauhan New
[v7,3/4] target/riscv: Expose sdtrig ISA extension Introduce sdtrig ISA extension - - - - --- 2024-03-14 Himanshu Chauhan New
[v7,2/4] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected Introduce sdtrig ISA extension - - 1 - --- 2024-03-14 Himanshu Chauhan New
[v7,1/4] target/riscv: Check for valid itimer pointer before free Introduce sdtrig ISA extension - - - - --- 2024-03-14 Himanshu Chauhan New
[v6,3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs Introduce sdtrig ISA extension - - - - --- 2024-03-14 Himanshu Chauhan New
[v6,2/3] target/riscv: Expose sdtrig ISA extension Introduce sdtrig ISA extension - - - - --- 2024-03-14 Himanshu Chauhan New
[v6,1/3] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected Introduce sdtrig ISA extension - - - - --- 2024-03-14 Himanshu Chauhan New
[v5,3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs Introduce sdtrig ISA extension - - - - --- 2024-03-13 Himanshu Chauhan New
[v5,2/3] target/riscv: Expose sdtrig ISA extension Introduce sdtrig ISA extension - - - - --- 2024-03-13 Himanshu Chauhan New
[v5,1/3] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected Introduce sdtrig ISA extension - - - - --- 2024-03-13 Himanshu Chauhan New
[v4,3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs Introduce sdtrig ISA extension - - - - --- 2024-03-13 Himanshu Chauhan New
[v4,2/3] target/riscv: Expose sdtrig ISA extension Introduce sdtrig ISA extension - - - - --- 2024-03-13 Himanshu Chauhan New
[v4,1/3] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected Introduce sdtrig ISA extension - - - - --- 2024-03-13 Himanshu Chauhan New
[v3,2/2] target/riscv: Export sdtrig in ISA string Export debug triggers as an extension - - - - --- 2024-02-29 Himanshu Chauhan New
[v3,1/2] target/riscv: Mark debug property as deprecated Export debug triggers as an extension - - - - --- 2024-02-29 Himanshu Chauhan New
[v2,2/2] target/riscv: Export sdtrig in ISA string Export debug triggers as an extension - - - - --- 2024-01-17 Himanshu Chauhan New
[v2,1/2] target/riscv: Convert sdtrig functionality from property to an extension Export debug triggers as an extension - - - - --- 2024-01-17 Himanshu Chauhan New
[2/2] target/riscv: Raise an exception when sdtrig is turned off Export debug triggers as an extension - - - - --- 2024-01-10 Himanshu Chauhan New
[1/2] target/riscv: Export sdtrig as an extension and ISA string Export debug triggers as an extension - - - - --- 2024-01-10 Himanshu Chauhan New
Add epmp to extensions list and rename it to smepmp Add epmp to extensions list and rename it to smepmp - - 1 - --- 2023-06-06 Himanshu Chauhan New
[v3] target/riscv: Smepmp: Return error when access permission not allowed in PMP [v3] target/riscv: Smepmp: Return error when access permission not allowed in PMP - 1 2 - --- 2023-06-05 Himanshu Chauhan New
[v2] target/riscv: Smepmp: Return error when access permission not allowed in PMP [v2] target/riscv: Smepmp: Return error when access permission not allowed in PMP - 1 - - --- 2023-06-05 Himanshu Chauhan New
target/riscv: Smepmp: Return error when access permission not allowed in PMP target/riscv: Smepmp: Return error when access permission not allowed in PMP - 1 - - --- 2023-06-05 Himanshu Chauhan New
target/riscv: Smepmp: Skip applying default rules when address matches target/riscv: Smepmp: Skip applying default rules when address matches - 2 2 - --- 2023-02-09 Himanshu Chauhan New