Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   1022 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
target/riscv: trans_rvv: Avoid assert for RV32 and e64 target/riscv: trans_rvv: Avoid assert for RV32 and e64 - - 1 - --- 2022-06-08 Alistair Francis New
target/riscv: pmp: Fixup TLB size calculation target/riscv: pmp: Fixup TLB size calculation - - 2 - --- 2022-10-12 Alistair Francis New
target/riscv: Call probe_write() before atomic operations target/riscv: Call probe_write() before atomic operations - - - - --- 2022-02-09 Alistair Francis New
hw: timer: ibex_timer: Fixup reading w/o register hw: timer: ibex_timer: Fixup reading w/o register - - 3 - --- 2022-01-10 Alistair Francis New
hw/riscv: opentitan: Fixup the PLIC context addresses hw/riscv: opentitan: Fixup the PLIC context addresses - 1 1 - --- 2021-10-25 Alistair Francis New
hw/riscv: boot: Reduce FDT address alignment constraints hw/riscv: boot: Reduce FDT address alignment constraints - - 2 1 --- 2022-06-08 Alistair Francis New
hw/riscv: boot: Don't use CSRs if they are disabled hw/riscv: boot: Don't use CSRs if they are disabled - - 1 - --- 2023-01-23 Alistair Francis New
hw/riscv: Enable TPM backends hw/riscv: Enable TPM backends - - 1 - --- 2022-04-01 Alistair Francis New
hw/intc: sifive_plic: Avoid overflowing the addr_config buffer hw/intc: sifive_plic: Avoid overflowing the addr_config buffer - 1 - - --- 2022-06-01 Alistair Francis New
[v5,6/6] hw/riscv: Enable TPM backends hw/riscv: Add TPM support to the virt board - - 2 - --- 2022-04-27 Alistair Francis New
[v5,5/6] hw/riscv: virt: Add device plug support hw/riscv: Add TPM support to the virt board - - 2 - --- 2022-04-27 Alistair Francis New
[v5,4/6] hw/riscv: virt: Add support for generating platform FDT entries hw/riscv: Add TPM support to the virt board - - 1 - --- 2022-04-27 Alistair Francis New
[v5,3/6] hw/riscv: virt: Create a platform bus hw/riscv: Add TPM support to the virt board - - 2 - --- 2022-04-27 Alistair Francis New
[v5,2/6] hw/core: Move the ARM sysbus-fdt to core hw/riscv: Add TPM support to the virt board - - 2 - --- 2022-04-27 Alistair Francis New
[v5,1/6] hw/riscv: virt: Add a machine done notifier hw/riscv: Add TPM support to the virt board - - 2 - --- 2022-04-27 Alistair Francis New
[v4,8/8] hw/riscv: virt: Allow support for 32 cores A collection of RISC-V cleanups and improvements - - 3 - --- 2022-01-05 Alistair Francis New
[v4,7/8] hw/riscv: Use error_fatal for SoC realisation A collection of RISC-V cleanups and improvements - - 3 1 --- 2022-01-05 Alistair Francis New
[v4,6/8] target/riscv: Enable the Hypervisor extension by default A collection of RISC-V cleanups and improvements - - 2 - --- 2022-01-05 Alistair Francis New
[v4,6/6] hw/riscv: Enable TPM backends hw/riscv: Add TPM support to the virt board - - 2 - --- 2022-04-20 Alistair Francis New
[v4,5/8] target/riscv: Mark the Hypervisor extension as non experimental A collection of RISC-V cleanups and improvements - - 2 - --- 2022-01-05 Alistair Francis New
[v4,5/6] hw/riscv: virt: Add device plug support hw/riscv: Add TPM support to the virt board - - 2 - --- 2022-04-20 Alistair Francis New
[v4,4/8] hw/intc: sifive_plic: Cleanup remaining functions A collection of RISC-V cleanups and improvements - - 1 - --- 2022-01-05 Alistair Francis New
[v4,4/6] hw/riscv: virt: Add support for generating platform FDT entries hw/riscv: Add TPM support to the virt board - - 1 - --- 2022-04-20 Alistair Francis New
[v4,3/8] hw/intc: sifive_plic: Cleanup the read function A collection of RISC-V cleanups and improvements - - 1 - --- 2022-01-05 Alistair Francis New
[v4,3/6] hw/riscv: virt: Create a platform bus hw/riscv: Add TPM support to the virt board - - 2 - --- 2022-04-20 Alistair Francis New
[v4,3/3] target/riscv: Implement the stval/mtval illegal instruction RISC-V: Populate mtval and stval - - 2 - --- 2021-12-20 Alistair Francis New
[v4,2/8] hw/intc: sifive_plic: Cleanup the write function A collection of RISC-V cleanups and improvements - - 1 - --- 2022-01-05 Alistair Francis New
[v4,2/6] hw/core: Move the ARM sysbus-fdt to core hw/riscv: Add TPM support to the virt board - - 2 - --- 2022-04-20 Alistair Francis New
[v4,2/3] target/riscv: Fixup setting GVA RISC-V: Populate mtval and stval - - 2 - --- 2021-12-20 Alistair Francis New
[v4,1/8] hw/intc: sifive_plic: Add a reset function A collection of RISC-V cleanups and improvements - - 2 - --- 2022-01-05 Alistair Francis New
[v4,1/6] hw/riscv: virt: Add a machine done notifier hw/riscv: Add TPM support to the virt board - - 2 - --- 2022-04-20 Alistair Francis New
[v4,1/3] target/riscv: Set the opcode in DisasContext RISC-V: Populate mtval and stval - - 2 - --- 2021-12-20 Alistair Francis New
[v3] target/riscv: Don't expose the CPU properties on names CPUs [v3] target/riscv: Don't expose the CPU properties on names CPUs - - 1 - --- 2022-06-08 Alistair Francis New
[v3,6/6] hw/riscv: Enable TPM backends hw/riscv: Add TPM support to the virt board - - 1 - --- 2022-04-19 Alistair Francis New
[v3,5/6] hw/riscv: virt: Add device plug support hw/riscv: Add TPM support to the virt board - - 1 - --- 2022-04-19 Alistair Francis New
[v3,5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines [v3,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 2 - --- 2021-08-30 Alistair Francis New
[v3,4/6] hw/riscv: virt: Add support for generating platform FDT entries hw/riscv: Add TPM support to the virt board - - 1 - --- 2022-04-19 Alistair Francis New
[v3,4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v3,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 3 1 --- 2021-08-30 Alistair Francis New
[v3,3/6] hw/riscv: virt: Create a platform bus hw/riscv: Add TPM support to the virt board - - 1 - --- 2022-04-19 Alistair Francis New
[v3,3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v3,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 2 - --- 2021-08-30 Alistair Francis New
[v3,2/6] hw/core: Move the ARM sysbus-fdt to core hw/riscv: Add TPM support to the virt board - - 1 - --- 2022-04-19 Alistair Francis New
[v3,2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines [v3,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 2 1 --- 2021-08-30 Alistair Francis New
[v3,2/2] target/riscv: Allow software access to MIP SEIP target/riscv: Allow software access to MIP SEIP - - 2 - --- 2022-03-17 Alistair Francis New
[v3,2/2] sifive_u: Connect the SiFive PWM device Add the SiFive PWM device - - 1 - --- 2021-09-09 Alistair Francis New
[v3,2/2] riscv: opentitan: Connect opentitan SPI Host [v3,1/2] hw/ssi: Add Ibex SPI device model - - 2 - --- 2022-03-03 Alistair Francis New
[v3,1/6] hw/riscv: virt: Add a machine done notifier hw/riscv: Add TPM support to the virt board - - 1 - --- 2022-04-19 Alistair Francis New
[v3,1/5] target/riscv: Expose interrupt pending bits as GPIO lines [v3,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - - 3 1 --- 2021-08-30 Alistair Francis New
[v3,1/2] target/riscv: cpu: Fixup indentation target/riscv: Allow software access to MIP SEIP - - 2 - --- 2022-03-17 Alistair Francis New
[v3,1/2] hw/timer: Add SiFive PWM support Add the SiFive PWM device - - 1 - --- 2021-09-09 Alistair Francis New
[v3,1/2] hw/ssi: Add Ibex SPI device model [v3,1/2] hw/ssi: Add Ibex SPI device model - - 2 - --- 2022-03-03 Alistair Francis New
[v2] target/riscv: Don't expose the CPU properties on names CPUs [v2] target/riscv: Don't expose the CPU properties on names CPUs - - 1 - --- 2022-06-01 Alistair Francis New
[v2] target/riscv: Call probe_write() before atomic operations [v2] target/riscv: Call probe_write() before atomic operations - - - - --- 2022-04-01 Alistair Francis New
[v2] hw: riscv: opentitan: fixup SPI addresses [v2] hw: riscv: opentitan: fixup SPI addresses - - 2 - --- 2022-02-18 Alistair Francis New
[v2,9/9] hw/riscv: virt: Set the clock-frequency A collection of RISC-V cleanups and improvements - - - - --- 2021-12-16 Alistair Francis New
[v2,8/9] hw/riscv: virt: Allow support for 32 cores A collection of RISC-V cleanups and improvements - - 3 - --- 2021-12-16 Alistair Francis New
[v2,7/9] hw/riscv: Use error_fatal for SoC realisation A collection of RISC-V cleanups and improvements - - 3 1 --- 2021-12-16 Alistair Francis New
[v2,6/9] target/riscv: Enable the Hypervisor extension by default A collection of RISC-V cleanups and improvements - - 2 - --- 2021-12-16 Alistair Francis New
[v2,6/6] hw/riscv: Enable TPM backends hw/riscv: Add TPM support to the virt board - - - - --- 2022-04-07 Alistair Francis New
[v2,5/9] target/riscv: Mark the Hypervisor extension as non experimental A collection of RISC-V cleanups and improvements - - 2 - --- 2021-12-16 Alistair Francis New
[v2,5/6] hw/riscv: virt: Add device plug support hw/riscv: Add TPM support to the virt board - - - - --- 2022-04-07 Alistair Francis New
[v2,5/5] hw/riscv: virt: Use the PLIC config helper function [v2,1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 1 --- 2021-10-22 Alistair Francis New
[v2,4/9] hw/intc: sifive_plic: Cleanup remaining functions A collection of RISC-V cleanups and improvements - - 1 - --- 2021-12-16 Alistair Francis New
[v2,4/6] hw/riscv: virt: Add support for generateing platform FDT entries hw/riscv: Add TPM support to the virt board - - - - --- 2022-04-07 Alistair Francis New
[v2,4/5] hw/riscv: microchip_pfsoc: Use the PLIC config helper function [v2,1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 1 --- 2021-10-22 Alistair Francis New
[v2,3/9] hw/intc: sifive_plic: Cleanup the read function A collection of RISC-V cleanups and improvements - - 1 - --- 2021-12-16 Alistair Francis New
[v2,3/6] hw/riscv: virt: Create a platform bus hw/riscv: Add TPM support to the virt board - - - - --- 2022-04-07 Alistair Francis New
[v2,3/5] hw/riscv: sifive_u: Use the PLIC config helper function [v2,1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 1 --- 2021-10-22 Alistair Francis New
[v2,3/3] target/riscv: Set mtval and stval support RISC-V: Populate mtval and stval - - - - --- 2021-09-08 Alistair Francis New
[v2,2/9] hw/intc: sifive_plic: Cleanup the write function A collection of RISC-V cleanups and improvements - - 1 - --- 2021-12-16 Alistair Francis New
[v2,2/6] hw/core: Move the ARM sysbus-fdt to core hw/riscv: Add TPM support to the virt board - - - - --- 2022-04-07 Alistair Francis New
[v2,2/5] hw/riscv: boot: Add a PLIC config string function [v2,1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 1 - --- 2021-10-22 Alistair Francis New
[v2,2/3] target/riscv: Implement the stval/mtval illegal instruction RISC-V: Populate mtval and stval - - 1 - --- 2021-09-08 Alistair Francis New
[v2,2/2] target/riscv: Allow software access to MIP SEIP target/riscv: Allow software access to MIP SEIP - - 2 - --- 2022-03-16 Alistair Francis New
[v2,2/2] sifive_u: Connect the SiFive PWM device Add the SiFive PWM device - - - - --- 2021-09-02 Alistair Francis New
[v2,2/2] riscv: opentitan: Connect opentitan SPI Host [v2,1/2] hw/ssi: Add Ibex SPI device model - - 2 - --- 2022-02-28 Alistair Francis New
[v2,2/2] hw: timer: ibex_timer: update/add reg address [v2,1/2] riscv: opentitan: fixup plic stride len - - 2 1 --- 2022-01-11 Alistair Francis New
[v2,1/9] hw/intc: sifive_plic: Add a reset function A collection of RISC-V cleanups and improvements - - 2 - --- 2021-12-16 Alistair Francis New
[v2,1/6] hw/riscv: virt: Add a machine done notifier hw/riscv: Add TPM support to the virt board - - - - --- 2022-04-07 Alistair Francis New
[v2,1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration [v2,1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration - - 2 - --- 2021-10-22 Alistair Francis New
[v2,1/3] target/riscv: Set the opcode in DisasContext RISC-V: Populate mtval and stval - - 1 - --- 2021-09-08 Alistair Francis New
[v2,1/2] target/riscv: cpu: Fixup indentation target/riscv: Allow software access to MIP SEIP - - 2 - --- 2022-03-16 Alistair Francis New
[v2,1/2] riscv: opentitan: fixup plic stride len [v2,1/2] riscv: opentitan: fixup plic stride len - - 2 1 --- 2022-01-11 Alistair Francis New
[v2,1/2] hw/timer: Add SiFive PWM support Add the SiFive PWM device - - - - --- 2021-09-02 Alistair Francis New
[v2,1/2] hw/ssi: Add Ibex SPI device model [v2,1/2] hw/ssi: Add Ibex SPI device model - - 1 - --- 2022-02-28 Alistair Francis New
[v2,1/1] hw/riscv: shakti_c: Mark as not user creatable [v2,1/1] hw/riscv: shakti_c: Mark as not user creatable - - 2 1 --- 2021-09-28 Alistair Francis New
[v1] include: hw: remove ibex_plic.h [v1] include: hw: remove ibex_plic.h - 1 1 - --- 2022-01-21 Alistair Francis New
[v1] hw: riscv: opentitan: fixup SPI addresses [v1] hw: riscv: opentitan: fixup SPI addresses - - 1 - --- 2022-02-16 Alistair Francis New
[v1,9/9] hw/intc: sifive_plic: Cleanup remaining functions [v1,1/9] hw/riscv: opentitan: Update to the latest build - - - - --- 2021-10-18 Alistair Francis New
[v1,8/9] hw/intc: sifive_plic: Cleanup the read function [v1,1/9] hw/riscv: opentitan: Update to the latest build - - 1 - --- 2021-10-18 Alistair Francis New
[v1,7/9] hw/intc: sifive_plic: Cleanup the write function [v1,1/9] hw/riscv: opentitan: Update to the latest build - - 1 - --- 2021-10-18 Alistair Francis New
[v1,6/9] hw/intc: sifive_plic: Add a reset function [v1,1/9] hw/riscv: opentitan: Update to the latest build - - - - --- 2021-10-18 Alistair Francis New
[v1,5/9] hw/intc: sifive_plic: Cleanup the irq_request function [v1,1/9] hw/riscv: opentitan: Update to the latest build - - 1 - --- 2021-10-18 Alistair Francis New
[v1,4/9] hw/intc: sifive_plic: Cleanup the realize function [v1,1/9] hw/riscv: opentitan: Update to the latest build - - 1 - --- 2021-10-18 Alistair Francis New
[v1,3/9] hw/intc: sifive_plic: Move the properties [v1,1/9] hw/riscv: opentitan: Update to the latest build - - 1 - --- 2021-10-18 Alistair Francis New
[v1,3/3] hw/riscv/microchip_pfsoc: Use the PLIC config helper function [v1,1/3] hw/riscv: virt: Don't use a macro for the PLIC configuration - - - - --- 2021-09-03 Alistair Francis New
[v1,2/9] hw/intc: Remove the Ibex PLIC [v1,1/9] hw/riscv: opentitan: Update to the latest build - - 1 - --- 2021-10-18 Alistair Francis New
[v1,2/3] hw/riscv/sifive_u: Use the PLIC config helper function [v1,1/3] hw/riscv: virt: Don't use a macro for the PLIC configuration - - - - --- 2021-09-03 Alistair Francis New
[v1,2/2] target/riscv: Set mtval and stval support RISC-V: Populate mtval and stval - - - - --- 2021-09-02 Alistair Francis New
[v1,2/2] target/riscv: Organise the CPU properties [v1,1/2] target/riscv: Remove some unused macros - - 2 - --- 2021-10-18 Alistair Francis New
[v1,2/2] riscv: opentitan: Connect opentitan SPI Host [v1,1/2] hw/ssi: Add Ibex SPI device model - - - - --- 2022-02-22 Alistair Francis New
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