Show patches with: Submitter = LIU Zhiwei       |    State = Action Required       |    Archived = No       |   1061 patches
« 1 2 3 4 … 10 11 »
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v4,18/20] target/riscv: Adjust vector address with mask Support UXL filed in xstatus 1 - - - --- 2021-11-11 LIU Zhiwei New
[v4,17/20] target/riscv: Fix check range for first fault only Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,16/20] target/riscv: Ajdust vector atomic check with XLEN Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,15/20] target/riscv: Remove VILL field in VTYPE Support UXL filed in xstatus 1 - 1 - --- 2021-11-11 LIU Zhiwei New
[v4,14/20] target/riscv: Adjust vsetvl according to XLEN Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,13/20] target/riscv: Fix RESERVED field length in VTYPE Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,12/20] target/riscv: Split out the vill from vtype Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,11/20] target/riscv: Split pm_enabled into mask and base Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,10/20] target/riscv: Calculate address according to XLEN Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,08/20] target/riscv: Create current pm fields in env Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v4,07/20] target/riscv: Adjust csr write mask with XLEN Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,06/20] target/riscv: Relax debug check for pm write Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,05/20] target/riscv: Use gdb xml according to max mxlen Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,04/20] target/riscv: Extend pc for runtime pc write Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,03/20] target/riscv: Ignore the pc bits above XLEN Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,02/20] target/riscv: Sign extend pc for different XLEN Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v4,01/20] target/riscv: Don't save pc when exception return Support UXL filed in xstatus - - 2 - --- 2021-11-11 LIU Zhiwei New
[v3,20/20] target/riscv: Enable uxl field write Support UXL filed in xstatus - - - - --- 2021-11-11 LIU Zhiwei New
[v3,19/20] target/riscv: Adjust scalar reg in vector with XLEN Support UXL filed in xstatus - - - - --- 2021-11-11 LIU Zhiwei New
[v3,18/20] target/riscv: Adjust vector address with mask Support UXL filed in xstatus - - - - --- 2021-11-11 LIU Zhiwei New
[v3,17/20] target/riscv: Fix check range for first fault only Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,16/20] target/riscv: Ajdust vector atomic check with XLEN Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,15/20] target/riscv: Remove VILL field in VTYPE Support UXL filed in xstatus 1 - - - --- 2021-11-11 LIU Zhiwei New
[v3,14/20] target/riscv: Adjust vsetvl according to XLEN Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,13/20] target/riscv: Fix RESERVED field length in VTYPE Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,12/20] target/riscv: Split out the vill from vtype Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,11/20] target/riscv: Split pm_enabled into mask and base Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,10/20] target/riscv: Calculate address according to XLEN Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,08/20] target/riscv: Create current pm fields in env Support UXL filed in xstatus - - - - --- 2021-11-11 LIU Zhiwei New
[v3,07/20] target/riscv: Adjust csr write mask with XLEN Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,06/20] target/riscv: Relax debug check for pm write Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,05/20] target/riscv: Use gdb xml according to max mxlen Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,04/20] target/riscv: Extend pc for runtime pc write Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,03/20] target/riscv: Ignore the pc bits above XLEN Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,02/20] target/riscv: Sign extend pc for different XLEN Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v3,01/20] target/riscv: Don't save pc when exception return Support UXL filed in xstatus - - 1 - --- 2021-11-11 LIU Zhiwei New
[v2,14/14] target/riscv: Enable uxl field write Support UXL filed in xstatus - - - - --- 2021-11-10 LIU Zhiwei New
[v2,13/14] target/riscv: Don't save pc when exception return Support UXL filed in xstatus - - 1 - --- 2021-11-10 LIU Zhiwei New
[v2,12/14] target/riscv: Split out the vill from vtype Support UXL filed in xstatus - - - - --- 2021-11-10 LIU Zhiwei New
[v2,11/14] target/riscv: Adjust scalar reg in vector with XLEN Support UXL filed in xstatus - - - - --- 2021-11-10 LIU Zhiwei New
[v2,10/14] target/riscv: Adjust vector address with mask Support UXL filed in xstatus - - - - --- 2021-11-10 LIU Zhiwei New
[v2,09/14] target/riscv: Relax debug check for pm write Support UXL filed in xstatus - - 1 - --- 2021-11-10 LIU Zhiwei New
[v2,08/14] target/riscv: Fix check range for first fault only Support UXL filed in xstatus - - 1 - --- 2021-11-10 LIU Zhiwei New
[v2,07/14] target/riscv: Ajdust vector atomic check with XLEN Support UXL filed in xstatus - - 1 - --- 2021-11-10 LIU Zhiwei New
[v2,06/14] target/riscv: Adjust vsetvl according to XLEN Support UXL filed in xstatus - - - - --- 2021-11-10 LIU Zhiwei New
[v2,05/14] target/riscv: Calculate address according to XLEN Support UXL filed in xstatus - - - - --- 2021-11-10 LIU Zhiwei New
[v2,04/14] target/riscv: Use gdb xml according to max mxlen Support UXL filed in xstatus - - 1 - --- 2021-11-10 LIU Zhiwei New
[v2,03/14] target/riscv: Extend pc for runtime pc write Support UXL filed in xstatus - - - - --- 2021-11-10 LIU Zhiwei New
[v2,02/14] target/riscv: Ignore the pc bits above XLEN Support UXL filed in xstatus - - 1 - --- 2021-11-10 LIU Zhiwei New
[v2,01/14] target/riscv: Sign extend pc for different XLEN Support UXL filed in xstatus - - 1 - --- 2021-11-10 LIU Zhiwei New
configure: Support modules for Windows configure: Support modules for Windows - - - - --- 2021-11-05 LIU Zhiwei New
configure: Support modules for Windows configure: Support modules for Windows - - - - --- 2021-11-05 LIU Zhiwei New
[13/13] target/riscv: Enable uxl field write Support UXL filed in xstatus. - - - - --- 2021-11-01 LIU Zhiwei New
[12/13] target/riscv: Don't save pc when exception return Support UXL filed in xstatus. - - 1 - --- 2021-11-01 LIU Zhiwei New
[11/13] target/riscv: Switch context in exception return Support UXL filed in xstatus. - - - - --- 2021-11-01 LIU Zhiwei New
[10/13] target/riscv: Adjust scalar reg in vector with ol Support UXL filed in xstatus. - - - - --- 2021-11-01 LIU Zhiwei New
[09/13] target/riscv: Adjust vector address with ol Support UXL filed in xstatus. - - - - --- 2021-11-01 LIU Zhiwei New
[08/13] target/riscv: Fix check range for first fault only Support UXL filed in xstatus. - - 1 - --- 2021-11-01 LIU Zhiwei New
[07/13] target/riscv: Ajdust vector atomic check with ol Support UXL filed in xstatus. - - - - --- 2021-11-01 LIU Zhiwei New
[06/13] target/riscv: Adjust vsetvl according to ol Support UXL filed in xstatus. - - - - --- 2021-11-01 LIU Zhiwei New
[05/13] target/riscv: Calculate address according to ol Support UXL filed in xstatus. - - - - --- 2021-11-01 LIU Zhiwei New
[04/13] target/riscv: Use gdb xml according to max mxlen Support UXL filed in xstatus. - - 1 - --- 2021-11-01 LIU Zhiwei New
[03/13] target/riscv: Ignore the pc bits above XLEN Support UXL filed in xstatus. - - 1 - --- 2021-11-01 LIU Zhiwei New
[02/13] target/riscv: Extend pc for runtime pc write Support UXL filed in xstatus. - - - - --- 2021-11-01 LIU Zhiwei New
[01/13] target/riscv: Sign extend pc for different ol Support UXL filed in xstatus. - - - - --- 2021-11-01 LIU Zhiwei New
target/riscv: Fix satp write target/riscv: Fix satp write - 1 2 - --- 2021-09-01 LIU Zhiwei New
[v2] target/riscv: Don't wrongly override isa version [v2] target/riscv: Don't wrongly override isa version - - 2 - --- 2021-08-11 LIU Zhiwei New
target/riscv: Don't wrongly overide isa version target/riscv: Don't wrongly overide isa version - - - - --- 2021-08-10 LIU Zhiwei New
[v2,1/1] target/riscv: Add User CSRs read-only check [v2,1/1] target/riscv: Add User CSRs read-only check - - 2 - --- 2021-08-10 LIU Zhiwei New
target/riscv: Add User CSRs read-only check target/riscv: Add User CSRs read-only check - - 1 - --- 2021-08-09 LIU Zhiwei New
target/riscv: Add User CSRs read-only check target/riscv: Add User CSRs read-only check - - - - --- 2021-08-09 LIU Zhiwei New
[RFC,13/13] target/riscv: Changing the width of U-mode CSR Support UXL field in mstatus - - - - --- 2021-08-05 LIU Zhiwei New
[RFC,12/13] target/riscv: Support UXL32 for RVB Support UXL field in mstatus - - - - --- 2021-08-05 LIU Zhiwei New
[RFC,11/13] target/riscv: Fix srow Support UXL field in mstatus - - - - --- 2021-08-05 LIU Zhiwei New
[RFC,10/13] target/riscv: Support UXL32 for float instructions Support UXL field in mstatus - - - - --- 2021-08-05 LIU Zhiwei New
[RFC,09/13] target/riscv: Support UXL32 for atomic instructions Support UXL field in mstatus - - - - --- 2021-08-05 LIU Zhiwei New
[RFC,08/13] target/riscv: Support UXL32 for vector instructions Support UXL field in mstatus - - - - --- 2021-08-05 LIU Zhiwei New
[RFC,07/13] target/riscv: Support UXL32 for RVM Support UXL field in mstatus - - - - --- 2021-08-05 LIU Zhiwei New
[RFC,06/13] target/riscv: Fix div instructions Support UXL field in mstatus - - - - --- 2021-08-05 LIU Zhiwei New
[RFC,05/13] target/riscv: Support UXL32 for shift instruction Support UXL field in mstatus - - - - --- 2021-08-05 LIU Zhiwei New
[RFC,04/13] target/riscv: Support UXL32 for slit/sltiu Support UXL field in mstatus - - - - --- 2021-08-05 LIU Zhiwei New
[RFC,03/13] target/riscv: Support UXL32 on 64-bit cpu for load/store Support UXL field in mstatus - - - - --- 2021-08-05 LIU Zhiwei New
[RFC,02/13] target/riscv: Support UXL32 for branch instructions Support UXL field in mstatus - - - - --- 2021-08-05 LIU Zhiwei New
[RFC,01/13] target/riscv: Add UXL to tb flags Support UXL field in mstatus - - 1 - --- 2021-08-05 LIU Zhiwei New
[v3,37/37] target/riscv: configure and turn on packed extension from command line target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,36/37] target/riscv: RV64 Only 32-bit Packing Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,34/37] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,32/37] target/riscv: RV64 Only 32-bit Multiply Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,27/37] target/riscv: Non-SIMD Miscellaneous Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,26/37] target/riscv: 32-bit Computation Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,25/37] target/riscv: Non-SIMD Q31 saturation ALU Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
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