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LIU Zhiwei
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Apply
«
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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
target/riscv: Fix vill field write in vtype
target/riscv: Fix vill field write in vtype
- - 2 -
-
-
-
2022-02-01
LIU Zhiwei
New
[v8,23/23] target/riscv: Relax UXL field for debugging
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,22/23] target/riscv: Enable uxl field write
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,21/23] target/riscv: Set default XLEN for hypervisor
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,20/23] target/riscv: Adjust scalar reg in vector with XLEN
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,19/23] target/riscv: Adjust vector address with mask
Support UXL filed in xstatus
1 - 1 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,18/23] target/riscv: Fix check range for first fault only
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,17/23] target/riscv: Remove VILL field in VTYPE
Support UXL filed in xstatus
1 - 1 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,16/23] target/riscv: Adjust vsetvl according to XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,15/23] target/riscv: Split out the vill from vtype
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,14/23] target/riscv: Split pm_enabled into mask and base
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,13/23] target/riscv: Calculate address according to XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,12/23] target/riscv: Alloc tcg global for cur_pm[mask|base]
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,11/23] target/riscv: Create current pm fields in env
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,10/23] target/riscv: Adjust csr write mask with XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,09/23] target/riscv: Relax debug check for pm write
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,08/23] target/riscv: Use gdb xml according to max mxlen
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,07/23] target/riscv: Extend pc for runtime pc write
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,06/23] target/riscv: Ignore the pc bits above XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,05/23] target/riscv: Create xl field in env
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,04/23] target/riscv: Sign extend pc for different XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,03/23] target/riscv: Sign extend link reg for jal and jalr
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,02/23] target/riscv: Don't save pc when exception return
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v8,01/23] target/riscv: Adjust pmpcfg access with mxl
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-20
LIU Zhiwei
New
[v7,22/22] target/riscv: Relax UXL field for debugging
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,21/22] target/riscv: Enable uxl field write
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,20/22] target/riscv: Adjust scalar reg in vector with XLEN
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,19/22] target/riscv: Adjust vector address with mask
Support UXL filed in xstatus
1 - 1 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,18/22] target/riscv: Fix check range for first fault only
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,17/22] target/riscv: Remove VILL field in VTYPE
Support UXL filed in xstatus
1 - 1 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,16/22] target/riscv: Adjust vsetvl according to XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,15/22] target/riscv: Split out the vill from vtype
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,14/22] target/riscv: Split pm_enabled into mask and base
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,13/22] target/riscv: Calculate address according to XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,12/22] target/riscv: Alloc tcg global for cur_pm[mask|base]
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,11/22] target/riscv: Create current pm fields in env
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,10/22] target/riscv: Adjust csr write mask with XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,09/22] target/riscv: Relax debug check for pm write
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,08/22] target/riscv: Use gdb xml according to max mxlen
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,07/22] target/riscv: Extend pc for runtime pc write
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,06/22] target/riscv: Ignore the pc bits above XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,05/22] target/riscv: Create xl field in env
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,04/22] target/riscv: Sign extend pc for different XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,03/22] target/riscv: Sign extend link reg for jal and jalr
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,02/22] target/riscv: Don't save pc when exception return
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v7,01/22] target/riscv: Adjust pmpcfg access with mxl
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-19
LIU Zhiwei
New
[v6,22/22] target/riscv: Relax UXL field for debugging
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,21/22] target/riscv: Enable uxl field write
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,20/22] target/riscv: Adjust scalar reg in vector with XLEN
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,19/22] target/riscv: Adjust vector address with mask
Support UXL filed in xstatus
1 - 1 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,18/22] target/riscv: Fix check range for first fault only
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,17/22] target/riscv: Remove VILL field in VTYPE
Support UXL filed in xstatus
1 - 1 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,16/22] target/riscv: Adjust vsetvl according to XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,15/22] target/riscv: Split out the vill from vtype
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,14/22] target/riscv: Split pm_enabled into mask and base
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,13/22] target/riscv: Calculate address according to XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,12/22] target/riscv: Alloc tcg global for cur_pm[mask|base]
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,11/22] target/riscv: Create current pm fields in env
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,10/22] target/riscv: Adjust csr write mask with XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,09/22] target/riscv: Relax debug check for pm write
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,08/22] target/riscv: Use gdb xml according to max mxlen
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,07/22] target/riscv: Extend pc for runtime pc write
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,06/22] target/riscv: Ignore the pc bits above XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,05/22] target/riscv: Create xl field in env
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,04/22] target/riscv: Sign extend pc for different XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,03/22] target/riscv: Sign extend link reg for jal and jalr
Support UXL filed in xstatus
- - 1 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,02/22] target/riscv: Don't save pc when exception return
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v6,01/22] target/riscv: Adjust pmpcfg access with mxl
Support UXL filed in xstatus
- - 2 -
-
-
-
2022-01-13
LIU Zhiwei
New
[v4,1/1] target/riscv: Fix PMP propagation for tlb
[v4,1/1] target/riscv: Fix PMP propagation for tlb
- - - -
-
-
-
2021-12-17
LIU Zhiwei
New
[v5,22/22] target/riscv: Enable uxl field write
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,21/22] target/riscv: Adjust scalar reg in vector with XLEN
Support UXL filed in xstatus
- - - -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,20/22] target/riscv: Adjust vector address with mask
Support UXL filed in xstatus
1 - 1 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,19/22] target/riscv: Fix check range for first fault only
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,18/22] target/riscv: Ajdust vector atomic check with XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,17/22] target/riscv: Remove VILL field in VTYPE
Support UXL filed in xstatus
1 - 1 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,16/22] target/riscv: Adjust vsetvl according to XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,15/22] target/riscv: Fix RESERVED field length in VTYPE
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,14/22] target/riscv: Split out the vill from vtype
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,13/22] target/riscv: Split pm_enabled into mask and base
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,12/22] target/riscv: Calculate address according to XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,11/22] target/riscv: Alloc tcg global for cur_pm[mask|base]
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,10/22] target/riscv: Create current pm fields in env
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,09/22] target/riscv: Adjust csr write mask with XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,08/22] target/riscv: Relax debug check for pm write
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,07/22] target/riscv: Use gdb xml according to max mxlen
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,06/22] target/riscv: Extend pc for runtime pc write
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,05/22] target/riscv: Ignore the pc bits above XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,04/22] target/riscv: Create xl field in env
Support UXL filed in xstatus
- - - -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,03/22] target/riscv: Sign extend pc for different XLEN
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,02/22] target/riscv: Don't save pc when exception return
Support UXL filed in xstatus
- - 2 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v5,01/22] target/riscv: Adjust pmpcfg access with mxl
Support UXL filed in xstatus
- - 1 -
-
-
-
2021-11-25
LIU Zhiwei
New
[v3,1/1] target/riscv: Fix PMP propagation for tlb
[v3,1/1] target/riscv: Fix PMP propagation for tlb
- - 1 -
-
-
-
2021-11-23
LIU Zhiwei
New
[v2,5/5] target/riscv: Modify return and parameter type for pmp_adjust_tlb_size
Check PMP rules num before propagation
- - - -
-
-
-
2021-11-22
LIU Zhiwei
New
[v2,4/5] target/riscv: Rename pmp_is_range_in_tlb
Check PMP rules num before propagation
- - - -
-
-
-
2021-11-22
LIU Zhiwei
New
[v2,3/5] target/riscv: Discard return value for pmp_is_range_in_tlb
Check PMP rules num before propagation
- - - -
-
-
-
2021-11-22
LIU Zhiwei
New
[v2,2/5] target/riscv: Give a more generic size for tlb
Check PMP rules num before propagation
- - - -
-
-
-
2021-11-22
LIU Zhiwei
New
[v2,1/5] target/riscv: Check PMP rules num before propagation
Check PMP rules num before propagation
- - 1 -
-
-
-
2021-11-22
LIU Zhiwei
New
target/riscv: Check PMP rules num before propagation
target/riscv: Check PMP rules num before propagation
- - - -
-
-
-
2021-11-16
LIU Zhiwei
New
[v4,20/20] target/riscv: Enable uxl field write
Support UXL filed in xstatus
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2021-11-11
LIU Zhiwei
New
[v4,19/20] target/riscv: Adjust scalar reg in vector with XLEN
Support UXL filed in xstatus
- - - -
-
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2021-11-11
LIU Zhiwei
New
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