Show patches with: Submitter = Anup Patel       |    State = Action Required       |    Archived = No       |   177 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v5,23/23] hw/riscv: virt: Increase maximum number of allowed CPUs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,22/23] docs/system: riscv: Document AIA options for virt machine [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,20/23] hw/intc: Add RISC-V AIA IMSIC device emulation [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,18/23] hw/intc: Add RISC-V AIA APLIC device emulation [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,17/23] target/riscv: Allow users to force enable AIA CSRs in HART [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,16/23] hw/riscv: virt: Use AIA INTC compatible string when available [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,15/23] target/riscv: Implement AIA IMSIC interface CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,14/23] target/riscv: Implement AIA xiselect and xireg CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,12/23] target/riscv: Implement AIA interrupt filtering CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,09/23] target/riscv: Implement AIA local interrupt priorities [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,07/23] target/riscv: Add defines for AIA CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,06/23] target/riscv: Add AIA cpu feature [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 2 - --- 2021-12-11 Anup Patel New
[v5,05/23] target/riscv: Allow setting CPU feature from machine/device emulation [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 2 - --- 2021-12-11 Anup Patel New
[v5,04/23] target/riscv: Improve delivery of guest external interrupts [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,03/23] target/riscv: Implement hgeie and hgeip CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - 1 2 - --- 2021-12-11 Anup Patel New
[v4,22/22] docs/system: riscv: Document AIA options for virt machine QEMU RISC-V AIA support - - 1 - --- 2021-10-26 Anup Patel New
[v4,21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine QEMU RISC-V AIA support - - - - --- 2021-10-26 Anup Patel New
[v4,20/22] hw/intc: Add RISC-V AIA IMSIC device emulation QEMU RISC-V AIA support - - - - --- 2021-10-26 Anup Patel New
[v4,19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine QEMU RISC-V AIA support - - - - --- 2021-10-26 Anup Patel New
[v4,18/22] hw/intc: Add RISC-V AIA APLIC device emulation QEMU RISC-V AIA support - - - - --- 2021-10-26 Anup Patel New
[v4,17/22] target/riscv: Allow users to force enable AIA CSRs in HART QEMU RISC-V AIA support - - 1 - --- 2021-10-26 Anup Patel New
[v4,16/22] hw/riscv: virt: Use AIA INTC compatible string when available QEMU RISC-V AIA support - - 1 - --- 2021-10-26 Anup Patel New
[v4,15/22] target/riscv: Implement AIA IMSIC interface CSRs QEMU RISC-V AIA support - - - - --- 2021-10-26 Anup Patel New
[v4,14/22] target/riscv: Implement AIA xiselect and xireg CSRs QEMU RISC-V AIA support - - - - --- 2021-10-26 Anup Patel New
[v4,13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs QEMU RISC-V AIA support - - - - --- 2021-10-26 Anup Patel New
[v4,12/22] target/riscv: Implement AIA interrupt filtering CSRs QEMU RISC-V AIA support - - 1 - --- 2021-10-26 Anup Patel New
[v4,11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs QEMU RISC-V AIA support - - - - --- 2021-10-26 Anup Patel New
[v4,10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 QEMU RISC-V AIA support - - - - --- 2021-10-26 Anup Patel New
[v4,09/22] target/riscv: Implement AIA local interrupt priorities QEMU RISC-V AIA support - - - - --- 2021-10-26 Anup Patel New
[v4,08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback QEMU RISC-V AIA support - - - - --- 2021-10-26 Anup Patel New
[v4,07/22] target/riscv: Add defines for AIA CSRs QEMU RISC-V AIA support - - - - --- 2021-10-26 Anup Patel New
[v4,06/22] target/riscv: Add AIA cpu feature QEMU RISC-V AIA support - - 2 - --- 2021-10-26 Anup Patel New
[v4,05/22] target/riscv: Allow setting CPU feature from machine/device emulation QEMU RISC-V AIA support - - 2 - --- 2021-10-26 Anup Patel New
[v4,04/22] target/riscv: Improve delivery of guest external interrupts QEMU RISC-V AIA support - - 1 - --- 2021-10-26 Anup Patel New
[v4,03/22] target/riscv: Implement hgeie and hgeip CSRs QEMU RISC-V AIA support - - 1 - --- 2021-10-26 Anup Patel New
[v4,02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs QEMU RISC-V AIA support - - 1 - --- 2021-10-26 Anup Patel New
[v4,01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode QEMU RISC-V AIA support - 1 2 - --- 2021-10-26 Anup Patel New
[v3,22/22] docs/system: riscv: Document AIA options for virt machine QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,20/22] hw/intc: Add RISC-V AIA IMSIC device emulation QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,18/22] hw/intc: Add RISC-V AIA APLIC device emulation QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,17/22] target/riscv: Allow users to force enable AIA CSRs in HART QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,16/22] hw/riscv: virt: Use AIA INTC compatible string when available QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,15/22] target/riscv: Implement AIA IMSIC interface CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,14/22] target/riscv: Implement AIA xiselect and xireg CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,12/22] target/riscv: Implement AIA interrupt filtering CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,09/22] target/riscv: Implement AIA local interrupt priorities QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,07/22] target/riscv: Add defines for AIA CSRs QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,06/22] target/riscv: Add AIA cpu feature QEMU RISC-V AIA support - - 2 - --- 2021-10-23 Anup Patel New
[v3,05/22] target/riscv: Allow setting CPU feature from machine/device emulation QEMU RISC-V AIA support - - 2 - --- 2021-10-23 Anup Patel New
[v3,04/22] target/riscv: Improve delivery of guest external interrupts QEMU RISC-V AIA support - - - - --- 2021-10-23 Anup Patel New
[v3,03/22] target/riscv: Implement hgeie and hgeip CSRs QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs QEMU RISC-V AIA support - - 1 - --- 2021-10-23 Anup Patel New
[v3,01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode QEMU RISC-V AIA support - 1 1 - --- 2021-10-23 Anup Patel New
[v2,22/22] docs/system: riscv: Document AIA options for virt machine QEMU RISC-V AIA support - - 1 - --- 2021-09-02 Anup Patel New
[v2,21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,20/22] hw/intc: Add RISC-V AIA IMSIC device emulation QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,18/22] hw/intc: Add RISC-V AIA APLIC device emulation QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,17/22] target/riscv: Allow users to force enable AIA CSRs in HART QEMU RISC-V AIA support - - 1 - --- 2021-09-02 Anup Patel New
[v2,16/22] hw/riscv: virt: Use AIA INTC compatible string when available QEMU RISC-V AIA support - - 1 - --- 2021-09-02 Anup Patel New
[v2,15/22] target/riscv: Implement AIA IMSIC interface CSRs QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,14/22] target/riscv: Implement AIA xiselect and xireg CSRs QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,12/22] target/riscv: Implement AIA interrupt filtering CSRs QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,07/22] target/riscv: Add defines for AIA CSRs QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,06/22] target/riscv: Add AIA cpu feature QEMU RISC-V AIA support - - 2 - --- 2021-09-02 Anup Patel New
[v2,05/22] target/riscv: Allow setting CPU feature from machine/device emulation QEMU RISC-V AIA support - - 2 - --- 2021-09-02 Anup Patel New
[v2,04/22] target/riscv: Improve fidelity of guest external interrupts QEMU RISC-V AIA support - - - - --- 2021-09-02 Anup Patel New
[v2,03/22] target/riscv: Implement hgeie and hgeip CSRs QEMU RISC-V AIA support - - 1 - --- 2021-09-02 Anup Patel New
[v2,02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs QEMU RISC-V AIA support - - 1 - --- 2021-09-02 Anup Patel New
[v2,01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode QEMU RISC-V AIA support - 1 1 - --- 2021-09-02 Anup Patel New
[v4,4/4] hw/riscv: virt: Add optional ACLINT support to virt machine QEMU RISC-V ACLINT Support - - 2 - --- 2021-08-31 Anup Patel New
[v4,3/4] hw/riscv: virt: Re-factor FDT generation QEMU RISC-V ACLINT Support - - 2 - --- 2021-08-31 Anup Patel New
[v4,2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT QEMU RISC-V ACLINT Support - - 2 - --- 2021-08-31 Anup Patel New
[v4,1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources QEMU RISC-V ACLINT Support - - 2 - --- 2021-08-31 Anup Patel New
[v3,4/4] hw/riscv: virt: Add optional ACLINT support to virt machine QEMU RISC-V ACLINT Support - - 2 - --- 2021-08-29 Anup Patel New
[v3,3/4] hw/riscv: virt: Re-factor FDT generation QEMU RISC-V ACLINT Support - - 2 - --- 2021-08-29 Anup Patel New
[v3,2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT QEMU RISC-V ACLINT Support - - 1 - --- 2021-08-29 Anup Patel New
[v3,1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources QEMU RISC-V ACLINT Support - - 2 - --- 2021-08-29 Anup Patel New
[v2,4/4] hw/riscv: virt: Add optional ACLINT support to virt machine QEMU RISC-V ACLINT Support - - 2 - --- 2021-07-24 Anup Patel New
[v2,3/4] hw/riscv: virt: Re-factor FDT generation QEMU RISC-V ACLINT Support - - 2 - --- 2021-07-24 Anup Patel New
[v2,2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT QEMU RISC-V ACLINT Support - - - - --- 2021-07-24 Anup Patel New
[v2,1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources QEMU RISC-V ACLINT Support - - 2 - --- 2021-07-24 Anup Patel New
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